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Recent content by downloadman

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    Question about calculating final data required time

    Re: [Clock Arrival Time] :smile: Thanks for the reply. Your reply answered my question.
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    [Design Compiler synthesis with various Process]

    Hi, Do we need to take care in teh synthesis, when we are going for 65nm synthesis to 40nm synthesis. Will there be any change in the tool optimization. The tool is design Compiler.
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    Question about calculating final data required time

    Re: [Clock Arrival Time] Hi Pavan, Thanks for the reply. In the report i have seen, if i have defined skew using the folloiwng command set_clock_uncertainity 0.1 [all_clocks] -- this means it is positive or negative skew ??? In the timing report, while calculatng data required time, this is...
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    Question about calculating final data required time

    Hi, I have observed in most of the pdfs that to calcuate final data required time, clock uncertainity (clock skew) will be subtracted from the clock period(cycle adjust) and clock network delay(source latency) is being added. Most of the times, source latency is defined as 0, but clock skew...
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    [Tcl to SDC Converter]

    Thanks for reply. If you can point to any exisiting conversion script, that will be great.
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    [Clock Constrain with Generated Clocks]

    Hi shitansh, Thanks for the reply. Your reply answers my first part of the question, by which i infer that I have to remove most the <create_generated_clocks> commands used to generate mux stage outputs. I will do that. The second part of the question, where i have mentioned to provide the...
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    [Tcl to SDC Converter]

    Hi all, Is there a way to convert .tcl to .sdc other than using DC :)? Regards Murali
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    [Clock Constrain with Generated Clocks]

    Hi, a) I have 4 primary clocks i.e clk1,clk2, clk3, clk4 to the design. b) There are two muxes to which these primay clocks are input to the muxes and one of the mux outputs will be fed to a divider. c) The divider output again is muxed with second Mux[First stage Mux] output. d) The...
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    What is a decoupling FIFO ?

    What is decoupling FIFO? Can any body share any architecture or knowabouts of the Same?
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    [ LEDA : RULE INFORMATION]

    Hi , I am using LEDA for linting. How can I view the Rule information from command line. eg. leda -help B_1102 like that... :cry:
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    Synchronous Resets in Scan Synthesis

    Hi , I have reset synchroniser module in my design. The asynchronous reset coming from top level is synchronised on different clocks generated internally. From that modules various resets flow to other modules of the design. I have declared reset signal in the scan command file by the...
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    [ Hookup ports in DFT compiler ]

    Hi All, Can anyone explain what is exactly hookup ports used in DFT compiler? I have to use in the following command : set_scan_signal .......... what type of signals that can be used a hookup pins.
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    Does Synopsys LEDA support commands like 'set_false_path'?

    Re: Does Synopsys LEDA support commands like 'set_false_path Hi wufei, You can give input the sdc file what Shitansh has provided using the command. LEDA meets ur requirement regarding false path. You can use gui instead of command line option, where u can get help easily. :)
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    Does Synopsys LEDA support commands like 'set_false_path'?

    Re: Does Synopsys LEDA support commands like 'set_false_path Hi, You can deselect a policy or rule by the following syntax : "rule_deselect -policy LEDA -ruleset CLOCKS -rule C_1202 " in the config.tcl file where you are mentioning the rules.If you dont have one, you can have one and put...

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