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Recent content by dogeatdog

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    Info on signal integrity issues in custom ASIC designs

    Re: Signal Integrity Some of the signal integrity issues are: 1. Crosstalk: Coupling capacitance between adjacent wires, wherein transitions in one wire may cause or inhibit transitions in another wire thereby leading to either noise, glitches or delayed transitions 2. IR-drop: Poor VDD or...
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    File format for (.lib) (.db) (.gds) (.clf) (.tdf) (.sdc)

    format tdf Hi, 1. A .sdc file is the Synopsys Design Constraints file. This is generally output by a synthesis tool such as Design Compiler or BG after synthesis of RTL to gates. In Design Compiler the command is write_sdc. This file contains all the timing and design constraints in an...
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    need help and tutorial for learning astro

    I have a cadence 0.18um library which contains 1. .lib file 2. .lef file 3. .tech.lef file (technology part of lef file) 4. .gds file (for standard cells) Can somebody provide some help on how to create a technology file (.tf) from these files (for astro-milkyway database). Has someone done...
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    Timing Requirements in SoC Encounter

    Hi If you have used BuildGates PKS or Design Compiler, you will be able to generate an (.sdc) file, which contains the timing constraints such as create_clock, set_input_delay, set_input_drive etc. The timing constraints file is generated only during synthesis, so you will have to use a...
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    need help and tutorial for learning astro

    Yeah, I have the tool. Can I know how to start this tutorial. Thanks
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    need help and tutorial for learning astro

    I have been trying to learn astro for a few weeks now. But I feel its learning curve is too high. Especially trying to prep all the libraries and databases is very confusing. I feel that it is not as easy to learn as say Encounter or Silicon Ensemble. I think there ought to be an easier method...
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    newbie: about pipeline design

    Refer to Giovanni De Micheli's book "Synthesis and Optimization of digital circuits" for details on functional pipelining of behavioral code. The points to be noted are: 1. Operations executing at concurrent times, will not share resources amongst one another whereas they can share with other...
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    Anyone have working rough DRC rules and tech files for 90nm

    drc rules I am trying to design a small standard cell library with 90nm cells.Can someone can give me pointers on how to write my own DRC rules for 90nm and also the technology file that is given to cadence virtuoso as input.If I have DRC rules for 180nm and 350nm, how can I modify them for...

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