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The SSRAM part is the IS61LPS512.
Here's the datasheet for the SSRAM part. It includes read/write timing diagrams a few pages into the sheet.
**broken link removed**
-Doc
Hello,
I built a small SSRAM controller for my DE2i-150 board and have noted two things that are odd about memory accesses when I connected up the VGA-LCD core. I have an OpenRISC SoC ported to this board. Under normal circumstances the test program I wrote to test out the SSRAM works as...
After looking more carefully at the differences between projects I did find a discrepancy with the input clock name between the two projects. The correct name was CLOCK_50 instead of CLOCK50. Before fixing the name everything still synthesized without any errors (I'm surprised at this). So I...
Thanks for pointing this stuff out. I'll take a look at the paper. I did run ModelSim on the code and it produced output that seemed reasonable (see screenshot).
I swapped over to developing out of the PCIE-Fundamental design example for the DE2i and am seeing inconsistent results when adding...
Hello, I have a deceptively simple problem with my Verilog code. I've simulated the first module and it appears to work when using blocking assignments in the initial block but not when using non-blocking assignments. When I synthesize the code for a DE2i-150 board I cannot seem to replicate the...
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