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Recent content by DocIng

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    Constraints in a design

    Every port, bus, clock, subdesign and constraints are stored as virtual foldersaccessible from RTL Compiler command window. the top level input ports are stored in /designs/TOP/ports_in clkin will be connected to CLK input of TOP module get_pins /designs/TOP/ports_in/CLK cannot find any pins.
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    Constraints in a design

    I used RTL compiler from cadence. define_clock -period 100000 -name clkin /designs/TOP/ports_in/CLK Error : A required object parameter could not be found. [TUI-61] [path_group] : An object of type 'instance|external_delay|clock|port|pin' named '' could not be found. : Check...
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    Cadence SoC encounter IN LINUX

    I am using RTL compiler Constraints a design define_clock -period 100000 -fall 80 -rise 80 -name clkin /designs/TOP/ports_in/CLK I have an error Error : A required object parameter could not be found. [TUI-61] [path_group] : An object of type 'instance|external_delay|clock|port|pin'...
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    Cadence SoC encounter IN LINUX

    I say that synthesis is a process from a software code lke verilog/Vhdl code to gate level netlist The input are behaviroal RTL/description ,technology library,design environements,design constraints The output optimised gate level netlist
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    Cadence SoC encounter IN LINUX

    I am using the rtl compiler to synthesize a verilog code the script of rtl compiler set_attribute lib_search_path my problem how I can choose the path of library ? set_attribute hdl_search_path . set_attribute library the target library? read_hdl...
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    Cadence SoC encounter IN LINUX

    Thanks you very much .I am the only one who works on the cadence tool, I am new in this field. that I find a lot of problem. - - - Updated - - - I am the first who will work on the cadence tool, I have no colleagues who can help me. I am very grateful to help me
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    Cadence SoC encounter IN LINUX

    I want to using RTL compiler from cadence to obtain gate level netlist from verilog code. I need the file synthesis.tcl ,I dont find it ; Should I build it?
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    Cadence SoC encounter IN LINUX

    Can you help me,I am new in cadence encounter. Have you any idea how to obtain gate level netlist utilisant cadence
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    Cadence SoC encounter IN LINUX

    For importing the different data for the design in SoC Encounter? need I instaling Synopsys design compiler ?
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    Cadence SoC encounter IN LINUX

    I run the cadence encounter. It is good; Can you help me how prepare the data to import design in Encounter How to prepare Gate level netlist (verilog) SDC constraint and IO constraint?
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    Cadence SoC encounter IN LINUX

    Hi I want to use cadence SoC Encounter in linux centos6 I need a tutorial how to use it. The command how to run it
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    Verilog Code for Networks on Chip NoC mesh 2D

    THanks your very. Have a verilog Noc.I want to tested it in modelsim in FPGA
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    Verilog Code for Networks on Chip NoC mesh 2D

    I need a powerful NoC (verilog code for a mesh NoC 2D) in order to validate a NoC DSP prototype on cadence. I am very grateful if you can help me
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    Cadence SoC encounter IN LINUX

    how to use Cadence Soc Encounter Hello, I' want to use Cadence Soc Encounter to validate a prtotyping design. I am very grateful if anyone can help me how can I use it. It seems me very difficult
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