Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
You'll need a Liberty model with statistical variation tables and statistical static timing analysis. If you have the correct spice models you can extract the critical path and simulate with monte-carlo analysis for a few paths. Of course, this isn't practical for a large number of paths.
interface_timing=true is used for arbitrary cells that don't have a function or state table description. The timing arcs are used as-is with no attempt to validate them against a function. As such, this is not the best way to model a latch. If it's simple just use a "latch" group. If you...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
