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Recent content by dipk11

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    Displaying report on Jenkins UI using data from Jenkins console for pipeline project

    I am new to jenkins. I have automated the building of the FPGA projects that are present in git and also automated some 3rd party syntax checker tests on the project. The Jenkins job console displays the outcome of the tests.It also generates the log file which has the summary of the tests run...
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    Jenkins CI/CD pipeline failure for a gitlab proj build.

    Hi i am new to using Jenkins CI/CD. I am using a Vnc server to connect to a remote Linux PC. I have a fpga project on gitlab which is cloned properly to my local repository. I used webhooks so that anything that is pushed inside the remote repository on the github, the jenkins script is...
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    Extracting data based on specific patterns in a text file using python

    Please help me!! I have a huge report file with some data where i have to do some data processing on lines starting with the code "MLT-TRR" For now i have extracted all the lines in my script that start with that code and placed them in a separate file. The new file looks like this- Rules.txt...
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    Makefile for FPGA poject-Vivado

    Hi I am new to creating makefile. I have written the following commands in a makefile but they do not seem to execute when i type make in my terminal. However, if i type the command seperately in the terminal, it works. The makefile contents are as follows. I am trying to open a vivado...
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    Simple C code for 50 point moving average filter using Buffer

    Hi all, Anybody has a code written for a N point moving average filter in C? I am basically stuck with the implementation when it comes to the averaging part. It would be great if someone can help me kickstart with sample code. Regards.
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    Running .elf file on ubuntu platform, Zynq Board

    Hi I am back after many days. I had not used the hostname for the connection. I had selected the USB port where the Board was connected. I am still facing problem connecting to the board.
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    Running .elf file on ubuntu platform, Zynq Board

    Thank you for replying... I am not sure how to connect to the snickerdoodle via the SCP software.. What do I enter as the hostname and the port number? Please see the images and the connection I use in teraterm to connect to the snickerdoodle.
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    Using a BFM in system verification code.

    Hi...I could do connections to the slave VIP. I could see the data that the master writes on the sdi line... Now my next task is to use the functions in available in the slave environment and get the data that is written by the master. The SysWip(http://syswip.com/) has two functions for the...
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    Using a BFM in system verification code.

    thanks for the reply..the tutorial did help me understand the interfaces in sv..but when i check the example codes provided by syswip and the tutorials...the connections and instantiation of the interface seems different. What I understand by now is...my master.sv file will be the top level...
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    Using a BFM in system verification code.

    Hi...explaining my doubt again..incase there is anybody who has used the IP before do help.. I have a master.sv file which has the code for SPI master. I have written a basic testbench (master_tb.sv)to test the master, but to simulate the SPI bus I wanted to use a verification IP already...
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    Running .elf file on ubuntu platform, Zynq Board

    Hi all, i am a newbie when it comes to embedded world. I somehow managed to download a prebuilt image on the zynq snickerdoodle development board. It boots up in ubuntu 16. I have generated a hello world program that prints Hello world from dolly on the console. I have chosen the platform as...
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    Using a BFM in system verification code.

    Thanks for your reply..i went through the user manual..it is okay to understand that...the example for spi looked really scary.. Just a clarification here, to test my master.sv file..i will have to import the slave interface right? Do the connections of my master port with the slave? I had...
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    Using a BFM in system verification code.

    Hi all, I am new to system Verilog and learning to write a test bench for already existing code. I have a master.sv file which has the code for SPI master. I have written a basic testbench (master_tb.sv)to test the master, but to simulate the SPI bus I wanted to use a verification IP already...
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    Reading x,y,z values from LIS3DH on interrupt using nrf52, sdk 15

    sorry, a small mistake in my previous reply. The interrupt comes even without shaking the device, same as that of 2g settings. Threshold register set to 0x80.
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    Reading x,y,z values from LIS3DH on interrupt using nrf52, sdk 15

    Hi andre, thanks for this suggestion. I tried setting it for 16g but the threshold value was difficult to set. I dont know the shiffting by 2 logic which you tolf. I set the value same. tHS=0x10 and the interrupt stopped coming. Even when i shake the device. Also the values that i get are a bit...

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