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Recent content by dipin

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    Run python on cyclone 5 soc

    hi, i created the client and server programs which will send numbers continuously, and i tested it and its working fie. But there is BIG PROBLEM. i am barely getting a speed of 1k. actually i need around 100k. i connected the fpga to a router through ethernet cable and laptop also connected to...
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    Run python on cyclone 5 soc

    Hi Swend, Yes i am using a linux on it, I need to transfer data from fpga to PC at 10k, Using the listening socket using C , can i make it possible,really sorry if my question is stupid. And thanks for the python information. I will gather more information about your C suggestion. thanks...
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    Run python on cyclone 5 soc

    hi, i have a cylone 5 sockit, which a c programming is running on arm processor generating 32 bit value at 10k rate. now what i wanted is to run a python inside the arm processor and implement "socket programming", so that with the help of ethernet, i can take out the live out at 10k rate to my...
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    Mismatched pcie lanes ip core vs hardware.

    hI, according to the pcie protocol , your question is about the physical layer. in physical layer specifically MAC layer. In MAC , there is a complex fsm called link training and status state machine (LTSSM). Which will configure all the link and lanes . (configure= assign link number,lane...
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    3 bit unsigned adder in behavioral verilog w a 4-bit sum

    HI, you can check how to display a number in 7 segment display thanks and regards
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    Problem understanding System Verilog

    Hi, from your working program, when you changes form this to this are you changing anything else ? (are you changing only this 3 lines of code ) thanks and regards
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    Sending data from dev/mem using mmap to PL side

    Hi, i had a zynq 7000 series Soc in my board. i am sending data from arm processor to PL side by opening "dev/mem" (it can access the physical address of the device ). this is my pl side : the axi_accelerator using an axi_lite with an address range of "8000_0000 to BFFF_FFFF" so using mmap...
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    Comparing two numbers

    hi, :smile: :confusion. so in post simulation give enough delay . you had only given 1 clockcycle delay. make it to 100 or above 100 and check your results again. I think you will be able to see all your outputs. thanks and regards
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    Comparing two numbers

    hi, with the above code how you are getting results at 10th clock cycle ? you are expecting output at 10th clock cycle right ? (in simulation) are you missing some delay in testbench? thanks and regards
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    AWS EC2 FPGA amazon cloud computing

    Thanks for the replay dzosgornik, its like high speed data processing. So if start developing in AWS and later i wants to move to FPGA, what will be the difficult level i will face ? thanks and regards
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    AWS EC2 FPGA amazon cloud computing

    Hi guys , Anybody here worked on Amazon EC2-F2 cloud. I wanted to work on it. So before that, thought of taking an opinion. How good it is ? (compared to the real FPGA ) i have gone through documents. Based on that , i think my target is SDAccel. Software to hardware interaction. Sending...
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    test bench for an Adder

    hi, quartus prime had a model-sim altera edition simulator. what TrickyDicky asking you is ::are you using the simulator to see the waveform or are you synthesizing the design? thanks and regards
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    PL to PS interrupt: how to access in ARM processor?

    Re: PL to PS interrupt:how to acess in arm processor hi, thanks for the replay niciki. i have a xc7z010 400g class 1 soc on my board . like other boards i dont have a usb jtag or serial cable . so i think i cant use sdk tools. so i was using memory map functions to map the output of PL to PS...
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    PL to PS interrupt: how to access in ARM processor?

    PL to PS interrupt:how to acess in arm processor hi. i am using a parallella fpga (which got zynq processor), which dont have jtag port. i had a custom ip and had a interrupt port in the custom ip. how can i get that interrupt in my arm processor. right now , i was getting the output of the...
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    Learning SystemVerilog

    Hi, why ? is there any recent trend in industry ? anyway for design we need to use only verilog right? not sv.. dont have much knowledge in sv, os if something like above, need to learn all those uvm, etc etc things (i dont have much industrial knowledge , thats why i am asking:shock:) thanks...
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