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hi what ius QRC
i am using cadence 5.141 with umc 180nm technology and assura
in the assura drop down box i have drc lvs erc and rcx but nothing called qrc...
can u let me know how to run it?????
looking forward to it
thank you......when simulating schematic i got a gain of about around 20...
well help me with this...
you suggested simulating the layout as i do to the schematic before extraction...
so i went to the config cell view and made the layout instead of schematic or av_extracted as the simulated view and tried the simulations but it is unable to create any netlists at all...
well i was trying to understand what ff or ss means..... after reading your post it seems it refers to doping conc...am i right...like due to process variations if the doping varies and i get a transistor with greater conc...thn how it will act...
thank you
how do i gnerate this view can u tell me the process to extact minus the parasites?
i created the netlist... but not much help there are numerous pcap but te largest in order of 10^-14...seems that wont be that much..
i understand the miller part...the compensation cap is a miller cap but...
how do u extract a layout without parasitics....are you refering to simulation of the schematic??
---------- Post added at 23:13 ---------- Previous post was at 22:55 ----------
a closer look at the post layout simulation results suggests that after layout my compensation capacitance has...
opamp post layout simulation... urgent very very urgent
hi i designed an opamp schematic....
on simulation the schematic is giving a gain of around 30dB
but after layout the post simulation result is bizarre....it is giving nearly 90dB....i was expecting tsome change in gain but how come the...
hi can anyone tell me how to set up corner analysis and monte carlo analysis??
why is it imp??
anyone got a manual of sorts or reading material on this??i will greatly appreciate any help
i saw that there are various models of the transistors fast fast fast slow typical....
how are we...
so i think i have to imagine in three dimension so the multiple column terminal is top layer
---------- Post added at 22:30 ---------- Previous post was at 22:25 ----------
thanks to all three of you
top[ plate as in layout.....
might sound silly but i am a bit confused
c when the layout appears the two column terminal is on the top of the screen and the multi column terminal at the bottom ...but if i think of the layers as one over anather....look at as if its been flattened in one...
i found those contacts to be via5.....
as u say will it connect to metal 1 i tried the connections are not working????
---------- Post added at 15:36 ---------- Previous post was at 15:36 ----------
sorry its vi5....say now its vi 5 how do i connect it to say poly or metal??
----------...
yes but then i can always create two nwell for two substrates in different potential and avoid shorts...
what i wanna ask is ....since i am not very sure how these poly res function.......i can understand that the poly is a material and a long strip of it will generate a resistance.
but how is...
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