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Re: VHDL - what is vmode ? a keyword i've never heard of?
Shared variables in VHDL -2008 are required to be protected types accessed by methods. Your shared variables won't work in -2008, also shared variables as protected types introduced in -2000 are not supported for synthesis. It would...
Re: verilog editor windows
Perhaps you could try a new Jedit? 4.4.2 does Verilog syntax highlighting window splitting code segment folding, indentation...
If you're not using an outdated version try Utilities->Global Options->Editing dialog or for a trying it out Utilities->Buffer Options...
I created a test bench for tra.vhdl (tra_test.vhdl):
--
-- tra_test.vhdl, test bench for tra.vhdl
--
-- supplies clock and reset
--
--
library ieee;
use ieee.std_logic_1164.all;
entity tra_test is
end;
architecture test of tra_test is
signal q: std_logic_vector (2 downto 0);
signal clk...
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