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Hi Bingo600,
I use a XSA-100 XESS board + XST-2 board, so I can't guarantee that my opinion is not biased.
I have no complaints whatsoever regarding the board or it's design. You can find many examples on XESS' site, some ready to use and the customer service is excellent, you will be talking...
fpga gsm
1) Does anyone know where to get GSM IP Cores and/or DSP software
for free? If this fails, then cheap or even expensive?
2) Also, I'd like to know what are the basic steps needed to build a
small GSM device capable of communicating with a GSM phone.
How hard is it? Can it...
Re: X_linx ISE 6.1i Problem
Git,
I have no constraints, I just created a new project with only this
file. Let me just ask you two questions:
- Are you synthesizing/implementing for the 2s100tq144-5 ?
- How do you set the environment variable? Do you do this as in:
Start -> Settings ->...
Re: X_linx ISE 6.1i Problem
ch_wen,
Here is an example of a VHDL code that generates the error
on my machine. Any ideas? Thanks, dingo.
library ieee;
use ieee.std_logic_1164.all;
entity test is
port(
dat_i : in std_logic;
dat_o : out std_logic
);
end test;
architecture arch of test...
Re: X_linx ISE 6.1i Problem
Hi guys,
Thanks for the answers. Inside ISE 6.1i, I switched the synthesizer to
Leonardo and it will synthesize OK, but the error now happens when
ISE tries to implement:
"
Started process "Map".
Using target part "2s100tq144-6"...
Re: X_linx ISE 6.1i Problem
Hi robotman,
Yes, you are right, I didn't specify. This error is generated with
or without SP1:
**broken link removed**
Thanks, dingo.
X_linx ISE 6.1i Problem
Hi there,
Every time I try to synthesize for the Spartan-2 in X_linx ISE 6.1i I get this message:
"FATAL_ERROR:DeviceResourceModel:basnpdevice.c:620:1.23 - bad nph file Process will terminate. To resolve this error, please consult the Answers Database and other online...
I suggest the XESS XSA-100 and XESS XST-2:
**broken link removed**
**broken link removed**
The boards' main highlights are:
- they have their own discussion forum on Yahoo;
- the people at XESS actually answer you when you have a question;
- there are many examples and projects ready for use...
verilog rs232 code
Jayson,
If you have access to Xilinx ISE, the "Hello World" example using the
XAPP223 can be put together using four files:
- the two .EDN files included in XAPP223;
- one VHDL file with all of your code;
- one .UCF file containing pin designations and your clock rate.
The...
rs232 xilinx
I found this on OpenCores:
Project: Serial Uart https://www.opencores.org/projects/miniuart2/
which is written in VHDL, but has two problems:
- no FIFO;
- no flow control.
There are other two projects written in Verilog, one is a complete 16550,
which seems to be kind of huge...
rs232 verilog code
Aircraft Maniac,
Thanks for your tip. I haven't been able to access OpenCores since
(at least) yesterday, looks as if they are down. I always avoid
OpenCores because people there tend to use Verilog, and I use VHDL.
I will wait until it is up.
Jayson,
Hmmm... The component...
rs232 flow control
I am trying to use the free reference design from Xilinx:
XAPP223 200MHz UART with Internal 16-Byte Buffer
**broken link removed**
I am having a hard time using it since it does not have the flow control
implemented, as when using RTS and CTS signals. How do you implement...
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