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I finally able to resolve this error.
The problem is when ever i was giving my library its not using the technology library that i dumped and modified.
Once i made changes to my .tf file, i created new library with the modified tech file.
Hello,
First I exported File-> export-> stream. and .lef file of inverter designed using cms9flp technology
Once the file were exported then i invoked abstract generator and i gave library, when i was trying to import gdsii file i am getting the following errors.
ERROR ABS-216: There are...
I am designing an ADC at high frequencies
As low vt has higher Power Dissipation compared to high vt so i thought hight vt is a good option.
But i would like to hear pros and cons who worked on them before
Everything is working good but the only problem is you didnt initialized the signal C..
I attached the simulated code and result
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_logic_unsigned.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with...
Well try this method ..
include condition_a and condition_b in process sensitive list
And by the way its really not a good idea to have 'X' as an output, works for the simulation but not when you are dumping the code on hardware
Hello All,
What exactly is the difference between the low Vt and high Vt ?
which one is most suitable for analog applications at high frequencies (2-5GHz)
Thank you!!
Hello All,
What exactly is the difference between the low Vt and high Vt ?
which one is most suitable for analog applications at high frequencies
Thanks to all who are eagerly waiting for questions to answer!!!
How to perform funtional simulation in tetramax?
I have been trying this since week but unsuccessful result..
If anyone who had tried it please share your knowledge.. it would be great help
Hi ,
this is my program
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity full_adder_4bit_2 is
port (a,b : in std_logic_vector(3 downto 0);
Cin : in std_logic;
S : out std_logic_vector(3 downto 0);
Cout: out std_logic);
end full_adder_4bit_2...
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