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Recent content by dinesh agarwal

  1. D

    how to use cadence to simulate PLL

    you can use PSS + PNOISE analysis, to simulate individual block phase noise.
  2. D

    How to add noise to PLL simulation in MATLAB?

    Re: PLL simulation in MATLAB Thanks i will search and try this one. But can i use the extracted data from my noise text file in VCO block available in simulink , if so pls give some details . thanks
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    How to add noise to PLL simulation in MATLAB?

    PLL simulation in MATLAB Hi everybody I have noise flie in text format of my VCO. How to add the noise in the simulink model of PLL using this text file. thanks
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    How to reduce or eliminate the phase noise hump?

    I think this is because of coupling of control voltage line with some signal of the offset frequency, resulting in the spurs.
  5. D

    using joinpins modify avParameter ASSURA LVS

    Hi, I have little problem during LVS run using joinPins parameter. Can someone help explaining joinPins option in case having 2vdd and 2gnd pins in schematic and layout thanks
  6. D

    Microwave Engineering

    i also need it avaiable at rapidshare but need password can someone tell the password
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    RF Lectures download from Berkley

    RF Lectures download EE142 lectures are available on Berkley webcast but icould only play online. Can anyone tell me how to download these webcast. Pls i need them thanks
  8. D

    PLL multiplication of variable frequency input

    understood your question: yes your PLL will provide multiplication of frequency crossponding to input variable frequency. But the lock time is limitation. You will not be able to get exact multipication if the locking time of your PLL is more than the time of frequency hop from one frequency...
  9. D

    Bining of parameters of BSIM model

    thanks for reply and you understood my doubt clearily umc 180nm uses model BSIM3v3. But in the BSIM3v3 manual i found some parameters mentioned as binable, hence the doubt. Do we realy use this option practically? or the present model incoporate this as limits for particular parameter.
  10. D

    Bining of parameters of BSIM model

    general doubt : Where we use the bining of binable parameters. Why to use what is the description which comple the use of binable parameters. very hopefull to get reply thanks
  11. D

    Delay circuit in PLL at the resest

    Actually inverter provide very small delay, Maybe you can use cap load to increase this delay. I think normally the delay taken is in neno sec. thanks
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    vedio lecture of RFIC design

    pls send me the link/source to get the below lecture. Urgently in need. https://webcast.berkeley.edu/course_details.php?seriesid=1906978242 Added after 1 minutes: Or any other RFIC vedio lecture download links. thank everybody
  13. D

    Noise simulation for NMOS using cadence spectre

    Noise simulation fo MOS Please forward procedure for noise simulation using cadence spectre for NMOS thanks
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    PCB DESIGN for INTEGER-N PLL BASED FREQUENCY SYNTHESIZERS

    MAY I REQUEST FOR HELP FOR PCB DESIGN FOR 2.4 GHZ FREQUENCY SYNTHESIZER. IF POSSIBLE CAN SOMEONE FORWARD THE EXEMPLARY PCB DESIGN
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    integer-N PLL locking - please guide to debug

    integer n pll +2009 the ratio control bits are checked and provide the ratio 495 correctly any other possibility
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