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If all you need is 3.3 to 1.2 the only difference is propagation delay and possibly some hard to define thresholds. If you need to send some signals back from 1.2 to 3.3 then the cross coupled one is a far better option
Andre,
Not every configuration will work well with inputs below the negative rail. The usual OPAMP has the CMIR > VTHP+VTHN+VOV to have all the transistors in active region
Hi Gentlemen,
I'm looking to design for the first time an OPAMP or OTA that can go little (100-200mV) below the negative rail that is gnda in my case. I want to avoid adding a charge pump.
I know the input pair and the mirror suppose to be in active region for a nice high performance OPAMP but...
The resistance is around 250k. I'm building multiple references.
That automatic calibration using the triode region sounds quite interesting. Could you give me more details ?
Thank you sir,
Thank you sir,
Right now my concern is just to calculate the best matching possible just as numbers. The layout will be a later concern. Right now it looks like using fab's matching data is hard to get where I want.
I did look at well resistors and indeed they have better matching but worse voltage effect. For poly, I got with huge numbers similar with yours and that is not feasible for my project. I'm looking for another method and if nothing works I'll use trimming.
Thanks
Hi Gentlemen,
I have a question that I found no answer yet.
In a normal bicmos process I want to match 2 poly resistors let's say better than 0.05%. According to the process data is almost impossible to get there only by increasing the size (not taking into consideration second order effects)...
Thank you all guys especially Dick_freebird.
Dick, yes, that was the idea I had too but there are some problem with submilivolt accuracy. If the current is low the noise is quite significant and if the current is higher it drains the cell.
Thanks
Hi All,
I need suggestions and ideas from the great guys I see helping here to build an analog circuit.
Briefly, my problem is to translate a cell voltage form a stack (battery) of fuel cells (as an example, my cell has the negative terminal at 20 V and the positive at 21.8 ).
The voltage I...
The differential pair with nmos input will steer the tail current function of the input voltage. Mi question is why the current gets unbalanced as the input transistors have the drains connected to pmos transistors connected as current mirror. When I look at the circuit it seems that the current...
It is not a stupid question. I think DGND pin is the most important. Vague formulated questions need a different approach in order to show your knowledge at an interview. Lets take it one by one:
1) Vcc -the microcontroller can be supplied by IO pin (check the IO schematic)
2) POR - might have...
Hello
Guys, I need suggestions for a reliable, internal brown out detector, that I can do with the few spare elements I have in an ASIC. The schematic with one pMOS or PNP and resistor divider it is OK, but I need something that gets less current or even zero in normal operation mode.
Any...
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