Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi,
I have a design in HFSS. I tried to import it to Altium because I want to design a PCB. The traces in altium are not filled. Note that I exported .dxf from hfss. I also tried exporting gerber but the traces are still not filled. Any idea how to fix this issue?
Regards,
Dima
Hello,
I got a question on what type of feedback loop does the ring oscillator (made of odd number of inverter) have? it is positive or negative feedback? and why?
I addition, the frequency of the ring oscillator= 1/2Nt. I know N is the number of inverters and t is the delay for each...
Hello,
Does anyone know if there is a formula to calculate the figure of merit of a dc-dc converter? I need to compare between my design and other designs regardless of details.
Regards,
Dima
You are right. I didn't know that I need to look at the net classes. The default minimum width was 0.3mm so that is why when I increased the trace width to 0.3mm the error was removed. It makes sense now. Thank you very much for your help. Appreciated!
I attached the photos. The first one where I have no trace routing and there is no error. The second photo is when I route, it gives me an error although the trace width>0.005mm as shown in the third photo. Now, i tried to increase the trace width to 0.3mm and the number of errors is reduced...
Hello,
I'm using eagle to design a PCB. In the layout, I got a width error. The trace width is 0.1mm and the minimum width is set to 0.005mm. I'm wondering where does this error come from?
I created another dummy layout and I use the same DRC setting as in the previous one and it has no...
Thanks for your reply. Now I got it and it does make sense. Will the SMD using the top layer for example creates a copper surface in the PCB? I know that the top layer is copper. Since I looked at different tutorials, I see people are using pads as shown in the attached figure which I think it...
I cant get your point. Do you mean that I dont have to use the bottom layer? if yes, why?
- - - Updated - - -
SMD pad have only two layers top or bottom. For example, if I used the top layer, will that create the electrical connection? Do I need to use the pad rectangle (with the green color)...
Hello,
I'm a new candidate in PCB design. I'm using eagle software. I've done the symbol for capacitor and now want to do the foot print.
I'm using SMD which is surface mount pad to create the two terminals of the capacitors. This SMD has two layers only which are the bottom (red) and top...
Do I need to consider that paddle as a pad/pin when drawing the schematic and the footprint? Or will I solder that paddle to the ground when doing the experiment?
Hello,
I'm designing now a PCB board for a certain system. One of the components is SAMB11 which consists of 48 pins/pads. However, the data sheet mentions that there is an exposed paddle that should be connected to the system board ground. I could not really understand this point!!
In the...
Yes, this how I measure the current consumption by average it.
I found one solution which might be useful. Itotla= Iactive+Ileakage. I measured Itotal by taking the average current. Ileak is measured when the inverter is off. Then Iactive=Itotal-Ileakage
Dear all,
I have designed a minimum inverter size in 65nm CMOS (W/L=150nm/60nm). I want to calculate the current consumption and leakage of the inverter.
I have two cases as below:
Case#1 (calculating total current): the input of the inverter is a normal clock (from 0V to Vdd). I measure...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.