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Recent content by DimaKilani

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    Importing from HFSS to Altium

    Hi, I have a design in HFSS. I tried to import it to Altium because I want to design a PCB. The traces in altium are not filled. Note that I exported .dxf from hfss. I also tried exporting gerber but the traces are still not filled. Any idea how to fix this issue? Regards, Dima
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    Feedback and frequency equation loop of ring oscillator

    Hello, I got a question on what type of feedback loop does the ring oscillator (made of odd number of inverter) have? it is positive or negative feedback? and why? I addition, the frequency of the ring oscillator= 1/2Nt. I know N is the number of inverters and t is the delay for each...
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    figure of merit for dc-dc converter

    Hello, Does anyone know if there is a formula to calculate the figure of merit of a dc-dc converter? I need to compare between my design and other designs regardless of details. Regards, Dima
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    Width DRC error in Eagle

    You are right. I didn't know that I need to look at the net classes. The default minimum width was 0.3mm so that is why when I increased the trace width to 0.3mm the error was removed. It makes sense now. Thank you very much for your help. Appreciated!
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    Width DRC error in Eagle

    I attached the photos. The first one where I have no trace routing and there is no error. The second photo is when I route, it gives me an error although the trace width>0.005mm as shown in the third photo. Now, i tried to increase the trace width to 0.3mm and the number of errors is reduced...
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    Width DRC error in Eagle

    Hello, I'm using eagle to design a PCB. In the layout, I got a width error. The trace width is 0.1mm and the minimum width is set to 0.005mm. I'm wondering where does this error come from? I created another dummy layout and I use the same DRC setting as in the previous one and it has no...
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    [Moved]: Pads, bottom and top layer in PCB design

    Thanks for your replay. Yes, I activated the other layers and I noticed pad is covered by tStop and tCream. That really helps :)
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    [Moved]: Pads, bottom and top layer in PCB design

    Thanks for your reply. Now I got it and it does make sense. Will the SMD using the top layer for example creates a copper surface in the PCB? I know that the top layer is copper. Since I looked at different tutorials, I see people are using pads as shown in the attached figure which I think it...
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    [Moved]: Pads, bottom and top layer in PCB design

    I cant get your point. Do you mean that I dont have to use the bottom layer? if yes, why? - - - Updated - - - SMD pad have only two layers top or bottom. For example, if I used the top layer, will that create the electrical connection? Do I need to use the pad rectangle (with the green color)...
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    [Moved]: Pads, bottom and top layer in PCB design

    Hello, I'm a new candidate in PCB design. I'm using eagle software. I've done the symbol for capacitor and now want to do the foot print. I'm using SMD which is surface mount pad to create the two terminals of the capacitors. This SMD has two layers only which are the bottom (red) and top...
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    ground pads in PCB design

    Thanks a lot. I was wondering that none of the 48 pins of the chip refers to ground. I think the paddle also used as the ground for the chip.
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    ground pads in PCB design

    Do I need to consider that paddle as a pad/pin when drawing the schematic and the footprint? Or will I solder that paddle to the ground when doing the experiment?
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    ground pads in PCB design

    Hello, I'm designing now a PCB board for a certain system. One of the components is SAMB11 which consists of 48 pins/pads. However, the data sheet mentions that there is an exposed paddle that should be connected to the system board ground. I could not really understand this point!! In the...
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    calculating the current consumption of the inverter

    Yes, this how I measure the current consumption by average it. I found one solution which might be useful. Itotla= Iactive+Ileakage. I measured Itotal by taking the average current. Ileak is measured when the inverter is off. Then Iactive=Itotal-Ileakage
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    calculating the current consumption of the inverter

    Dear all, I have designed a minimum inverter size in 65nm CMOS (W/L=150nm/60nm). I want to calculate the current consumption and leakage of the inverter. I have two cases as below: Case#1 (calculating total current): the input of the inverter is a normal clock (from 0V to Vdd). I measure...

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