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Re: One Clock Pulse?
Thanks for the help guys. I figured it out. The protocol was something like this, I receive a req pulse, perform a read or write operation, then send read data and an ack pulse back after the transaction. The requester, will take in the read data when acknowledge is...
Re: One Clock Pulse?
Unfortunately, that does not help me any because I do not have a stack like structure. I am not sure how to generate a pulse that stays high for one clock cycle and goes low again. Any other suggestions would be appreciated. Thanks.
One Clock Pulse?
I am coding up an interface in verilog that requires me to send an acknowledge pulse signal that remains high for one clock period. I am stuck on how to do this. Any pointers?
Thanks for the responses. I don't think I phrased my question correctly. I wanted to shift out all the bits of the input into q. So basically a parallel to serial type application. L0gik's solution was the work around. Thanks for the help!
input [3:0] d;
input clk,rst;
logic [3:0] hold;
always @(posedge clk)
begin
if(rst) hold <= 0;
else
hold <= d >>1;
end
assign q = hold [0];
Can someone tell me why this only shifts once and not every clock edge?
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