Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
LM158 has real weak sink current and from looking at layouts I can see that every vendor has a different compromise (and often over a series of cut-and-try, leaving unconnected devices). The load resistor is recommended because Sink is so weak.
Almost any op amp is better than LM158. Its only...
Low value resistors likely have more film thickness so maybe more power-to-blow. Over some range for a given film thickness you can play with L/W but when either of those gets stupid small (also affecting close-in thermal mass of the current carrying material hence power-to-blow pulsed or steady...
For mature TSMC flows it looks like there's some third
party ESD IP to be had, though in skimming some not-
so-mature-looking details (like needing waivers) can be
seen. If you mean to lay out your own this sarch phrase
turns up some design-and-results type papers too
tsmc esd 180
I like having valid (incl abnormal conditions) models
so I can -design- protection per pin.
A basic MOSFET model for a GGNMOS clamp has
little use because MOS models don't do breakdown.
You have to macromodel it. But after doing the work
(models & methods) we started meeting part ESD
goals...
Stripes. Lots of stripes. Pay attention to electromigration and
layout, current flow. Make finger width no wider that what a
drain finger metal width over topography can support for
peak and average max current spec, unless you are sure
you can take it out vertically to fatter Met2 (and use...
Sometimes I see ESD libraries and sometimes I don't, not a
TSMC user. If you want information for -a- specific process
then you need to say which (and more than a yes/no, probably
need to go to the foundry as every customer is NDA'd up.
If there is no ESD library then ESD protection is made...
The kit name makes me think it's for a 6LM process and
maybe via7 is not valid for the PDK sub-flow variables
as set.
Like right now for another foundry I've got a device library
with MIM caps but it won't even let me place them due to
some callback logic saying I don't have the flow with...
Are you receiving a companion clock from the same
source as the data, aligned ideally? That would be best.
Otherwise you have to recover clock from data and that
gets busy, quick.
There are two or three stable states of this simple PTAT.
Off, current-locked and in the case of its bipolar cousin,
possibly a higher current caused by the reference devices
N and P saturating and messing up the mirror gain in a
"runaway until you hit the wall" sort of way.
Of course if you...
High moisture is not your friend here, and portland cement binds plenty of that, and will let it go when hot, ruining its adhesion and maybe more corrosion.
Frit is mineral-fluxed glass and aside from the borax's bound water (which will drive off) will "freeze" really chemically stable. I think...
Bias that counters transistor behavior (such as PTAT
fighting gm (mobility) reduction w/ temp) can give a
better result than a fixed voltage (LDO, bandgap) if
you get the tempcos to "wash".
Whoever said "two wrongs don't make a right" never
did analog circuit design.
If you have a good guess at layout then do a plate or line capacitance calc. Then use pcapacitor elements for the loading (and do not neglect cross coupling or co-routed lines).
pcapacitors are neglected at LVS so won't bother that if you leave them in by neglect. If you use a variable in the...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
