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Re: RC settling and the miller effect
Thanks guys. I see things clearer now. With the settling case I am looking at a DC offset as the voltage on one side of the cap is clamped to a reference value
where as for the miller effect the voltages on both sides are varying giving rise to a varying...
Here is a question which has been bothering me about caps:
1.) Charge stored on a cap is given by Q = C. V. Therefore if I double the voltage across a cap, I double
the amount of charge it can store hence doubling its effective capacitance. This is the idea behind the
Miller effect...
Hi All,
I have a folded cascode OTA with PMOS input diff pair. Just
like the attached excepte with CMFB from "voutn" to "vbp2".
Pretty standard architecture. I can see how M4A increases output
impedance but am a little confused as to exactly how M2A increases output
impedance.
Is this NMOS...
Thanks. After a day with the system, yes I would redefine PM:
PM = 180 - the minimum phase between 0 -> GBW.
Only for a 2 pole system where any zero's or higher order poles occur at > 10xGBW should the following definition be used:
PM = 180 - the phase at GBW.
As for GM, yes I agree. A...
Hello all,
My question is best illustrated with the below example I am seeing for my system:
At the GBW, the phase response is 55deg from the 180deg pt. This would imply a phase margin (PM) of 55deg.
However: At a frequency < GBW, my phase response dips to 40deg (LHP zero present).
=> Is the...
Thanks that makes sense.
Just to make sure Im am understanding clearly:
Say I have an NMOS diff pair. The -ve terminal NMOS has a Vt shifted by +2mV.
=> Avol is max when Vin(-ve) is +2mV above Vin(+ve).
If both Vts were the same (and ignoring other offset sources), Avol would be max when...
Hello all,
I understand that the larger the gain the less the effect of offset since the more its impact on the output is supressed.
But does offset itself reduce gain?
Say my input diff pair contributes significant Vt mismatch leading to offset. Would this reduce my Aol?
Thanks,
Diarmuid
Thanks guys. Process variability makes sense.
Also worth mentioning that supply rejection will be worse if PMOS biases NMOS or vice versa.
Thanks,
Diarmuid
Yes you both are correct (there was a small bug in my tb).
At DC both are the same but as frequency increases they start to deviate by a couple of dB.
Thanks for the help,
Diarmuid
Hi guys,
When biasing a PMOS cascode, I always see it done using a PMOS diode i.e. PMOS diode connected to a current sink.
When biasing an NMOS cascode, I always see it done using an NMOS diode i.e. NMOS diode connected to a current source.
What would be the implications if I mixed up the...
Thanks for the responses. So Ive attached the circuit I am seeing PSRR = GSRR at DC.
Its a standard V2I circuit which takes in 1V and generates a current from this across a resistor. The OTA
is folded cascode with NMOS input diff pair and vssa referred CMFB. PSRR / GSRR measurements are
made...
Hi all,
PSRR = rejection of disturbance from power line
GSRR = rejection of disturbance from ground line
In my simulations both PSRR and GSRR results are identical.
Is this correct and if so why?
Thanks,
Diarmuid
Yes, as described in Willy Sansens Analog Design Essentials: PSRR = Avol/Avdd. In my case, my Avol was 90dB but my Avdd was 10dB (output stage of opamp was gaining up the noise seen
at the output). This is where the 10dB was going.
Hello All,
Just wondering if anyone has an explanation for this:
I am looking at the PSRR at DC of a V2I converter, basic schematic attached.
The loop gain at DC is 90dB. However, my PSRR at DC (taken at the top of the resistor) is 80dB.
Does this make sense? I would have thought the PSRR...
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