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@BradtheRad: Qs are not similar. The thread u mentioned is about xilinx ISE simulation error. My question is about Synopsys vcs. And in my case the simulation is working fine but dve wave dump is not created properly.
I compiled my verilog codes with test bench files using vcs command. Then ./simv command is used to run simulation and it is also running without no errors and giving expected display messages in command window. vpd dump file is also created(amount of bytes of the vpd file is very low - 22KB)...
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