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vlsi application
Very true.
The time has come where more important is the idea of using(degree of applicability) than performance....
I think we already reached a speed limitation...
So until there are other solutions in terms of speed (and consumption), we must channel our attention on more...
ideas to present good projects
Hi Pini_1,
Is your address still active? ( "http://bknpk.no-ip.biz/usb_1.html" ) I can't access it...
NOw I can...Thanks very GOOD SITE :D
Thanks all :)
Hello, I composed a schematic in Vituoso with 2 TG(4 transistor at all), these transmission gates are in series connected (from in to out). And between them, I placed a capacitor, lets say 10pF (or 50pF) to ground. The switches are driven from an non-overlapping generator( made by 2 'vpluse'...
vlsi future
I think it's because of the economical crisis. I don't know how much time it will take.... I don't think VLSI domain will fall today because, everything high tech will need VLSI, and the people are starved about high tech. Probably now it's a dark period in this domain, but I...
Hello, I know some books about Digital design flow :
1) Digital Integrated Circuits (2nd Edition) by Jan M. Rabaey
2) CMOS Logic Circuit Design by John P. Uyemura (a very good book,by my opinion)
But there are many book about digital design, you can search the amazon, to make an idea...
questasim batch mode
If I'm not mistaking , Tools -> Coverage -> Reports. At path input box, u will put the name of the report file.
OR
in command line :
coverage report -file file.txt
I hope it's useful for you....
Have a nice day to all,
Dexter
encounter test
Hello all, Is Encounter Test different from SoC Encounter ? And what is the acronym ? And where can I find some Documantation about it...?
Thanks in advance,
Dexter.
Yes, true.... the simulator will show you a X (unknown) , so you must somehow set a state to the counter, in reality , the counter will count. If no reset, you can divide simply with an AND gate between (LSB)bit and (LSB+1)bit...
Sorry for this kind of questions, but I DO need to make an idea about something:
Nowadays , which is more in demand(wanted) ?
1) Digital Design in HDL
2) Hardware verification in HVL
3) Digital synthesis
4) P & R including timing constraints
5) Custom Layout
I know that...
Well I think for synthesis (from Cadence) you can use BuildGates (bg_shell or pks_shell, you'll have the Ambit std_cells) or RTL Compiler (RC - I've never used this tool, I wish too ). And if you want, you can use DesignCompile (DC from Synopsys).
You can synthesis with Xilinx too (you can...
Yes, but if I'm not wrong, first you must synthesis from RTL code to gate level. And try to save it as EDIF type. Probably there is a better solution, but I can't think of something else right now.
Re: CMOS Inverter
I don't think it will oscillate, even in practical mode, because the oscillation frequency it will be so high, but the inverter has 2Cgs which brings two poles at pretty low freq compared with the oscillating freq....
Anyway, if we consider it will start to oscillate...
Verification Methodology
Hi all, I'm new in this domain, so my question is where can I find some documentation about Verification Methodology (for the moment,regarding Functional verification and Formal verification). And I need some examples too.
Thanks in advance,
and
Have a nice day !
Hello , so you said that you can't open with a "particular verilog file" , and if the problem it's not about the license, than perhaps the file is opened in read-only mode, because you don't have write permissions or maybe the file have +x(executive permissions) on it. I've encountered the same...
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