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The diagram drawn by my teacher and attached in the previous post calls for a NAND gate with 3 inputs. The third input is for the "Preset" and "Reset" at NAND gates 3, 4, 7, and 8 in the diagram (from left to right)
I tried to convert the 3 input NAND gate into two 2 input NAND gates but...
Ok, last question, I promise!
What's wrong with my Flip Flop? My output for Q and Q' are both x. Any ideas why?
module flipflop(output q,
output q_not,
input p,
input d,
input c,
input r);
wire [1:0]...
I have to do the barrel shifter at the gate-level as part of my assignment.
I'm only implementing the left barrel shifter for now, then I will implement the right barrel shifter after I can get the left one working first. Once both the left and right side are implemented, I can combine them...
Thanks for the link, but I know how to use a generate block :)
The problem I'm having is the algorithm inside the for-loop for placing the 0's and output from previous cascaded muxes
Sorry for being clueless, but how could I verify the next input? I only know how to verify Q(t) and not Q(t+1)
Here's the test bench I wrote using inputs from the truth table:
module sr_latch_test;
wire q;
wire q_not;
reg s;
reg c;
reg r;
sr_latch test1(.q(q), .q_not(q_not)...
I'm having some trouble thinking of an algorithm for extending a 4-bit left shifter to 32-bits
Here's my 4 bit left shifter code:
module left_barrel_shift_4(output [3:0] y,
input [3:0] b,
input [1:0] s);
wire mux1_out, mux2_out...
Hey everyone! Would greatly appreciate it if someone could look over my code and tell me if I implemented this correctly.
1-bit SR-Latch: (Teacher provided the diagram and truth table)
Code here: (c is for the clock)
module sr_latch(output q,
output q_not...
Hey all,
I was wondering if you could help me with my homework.
I need to implement a 4-bit multiplier at the gate-level in verilog using AND gates and adders
I've drawn the layout, but I'm having trouble translating it to Verilog.
When I instantiate an AND-gate, how do I extract the least...
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