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Recent content by dehati

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    SMT Prototyping Board - Mono SMT-Proto

    The Mono SMT-Proto , has a clever design using which you can connect pins of most popular IC package to a Pull Up, Pull Down, VCC, GND or any other Pin. Once you do that you can interconnect the ICs using wires on the bottom surface. Finally the board is powered by USB - so you can give 5V or...
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    [moved] Spartixed : Low cost evaluation board to learn Verilog / VHDL

    Kickstarter has $29 Spartan 6 board to help you learn FPGA, Verilog / VHDL and comes with with I2C, UART, SPA, LED. I hope this is something that will be of interest to the community. Please see https://www.kickstarter.com/projects/1728237598/spartixed-fpga-board-to-learn-verilog-vhdl
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    Does my board qualifies as high speed PCB?

    Tech-etch is really good in providing cost effective solutions. If you need any kind of shielding in US they are the first guys that come to my mid. However, the 4 layer solution could be more cost effective, provided it is done properly. Shielding is often done as an added protection for RF...
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    Does my board qualifies as high speed PCB?

    One of the things that I will be careful is the loop area of the return current of all the high speed signals. This has the potential to create EMI and cross talk issue. 2 Layer board may work provided, you can visualize the return path of all critical signals and make sure that the loop area...
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    90 degree traces routing

    A right angle bend creates additional capacitance and there will be slight amount of capacitive reflection. However, this reflection is of the order of less than 0.05 pf and can be ignored in most cases. The calculation at http://referencedesigner.com/books/si/ch16_5.php shows that the...
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    Combinational circuit with RF Module

    You may like to check existing SPI code ( in verilog or VHDL as the case may be) and see how you can use it to interface with the RF nodule. SPI interface comes under sequential circuits and a combinational only device will not work.
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    better ways to clock divisions

    The PLLs will be device specific and you will need to consult the individual chip implementation for that. The Code to divide a clock will be independent of it and solves some issue as synchronization. However, for high clock frequency they will generate a large amount of jitter. If you wish to...
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    Instiating submodules in verilog

    See this complete working example here - basically there were two sets of issues in the code.
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    PCB Designing Jobs & Interview questions

    Good suggestions from members. I found this one helpful. https://starredreviews.com/interview-questions-for-pcb-design-engineer-job/6850/
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    is it my gerber output from allegro true?

    This tutorial shows the steps required to generate gerber in Allegro. http://www.referencedesigner.com/tutorials/allegro/allegro_page_9.php If you follow this you should be good to go.
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    Question Regarding the Knee Frequency in High Speed Digital Design

    Check out this one http://referencedesigner.com/books/si/Knee-frequency.php
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    Calculate trace width for all layers?

    For Stripline use this calculator http://referencedesigner.com/tutorials/si/si_07.php For microstrip use this one http://referencedesigner.com/tutorials/si/si_06.php
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    allegro PAD & footprint

    This one is the best tutorial to get started on Allegro http://www.referencedesigner.com/tutorials/allegro/allegro_page_1.php
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    orcad pcb editor BEGINNER

    Yes, you need to create all the footprints before you start routing. You may also delete part of the Schematics and add the components one by one.
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    [SOLVED] Allegro 16.6 Pin Renumbering Options

    I think this is a good solution. Also has a youtube showing how to do it. Should not take that long. http://www.referencedesigner.com/tutorials/allegro/allegro_page_24.php

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