Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Can some one plz suggest me that is the give condition below are same in verilog
1) always @(posedge clk)
a=a+1'b1;
2) always @(clk)
if(clk==1'b1)
b=b+1'b1;
if these two always blocks are in the same program, are these both always blocks are the same or they give different...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
