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Recent content by deepthi_nach

  1. D

    Usage of always inside a function in Verilog

    how to declare bit vector signals in verilog? like i need, input [0:2] portin [0:2]; how can this declaration be done?
  2. D

    spectre analog environment errors

    thanks. I completed it.
  3. D

    Usage of always inside a function in Verilog

    can we use always inside an always block?
  4. D

    spectre analog environment errors

    1. error found by spectre during circuit read-in "/models/spectre/gpdk.scs" 7: illegal library definition found in netlist 2.error found by spectre in 'xjvar_nf36'during circuit read-in "/models/spectre/xjvar_nf36.scs" 14: xjvar_nf36 is being redefined 3.error found by spectre in...
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