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Recent content by decibel08

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    help identify failure mode of SMPS?

    Yes, the second photo is the cover. This PSU is a single output, so all 140W should be available to the 24V output. I'm thinking the main problem was using the max output (5A) but only one effective wire and a single crimp. Both the 22AWG and the crimp are iffy at 5A although technically...
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    help identify failure mode of SMPS?

    Attached is a picture of a failed PSU that was providing 24V at 5A on the red lead. PSU is rated for 140W so it should be able to handle this. There are obvious burn marks on the metal chassis above the connector, and also a strange white fuzz on nearby metal surfaces inside the case (might be...
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    simple 10mA current current sink IC ?

    I want to incorporate a 10mA constant current sink into a design as a sort of dummy load to bias a larger current driver. I found the Texas Instruments REF200 but it only sinks 100uA. Then I also found the NXP PSSI2021SAY but it is unclear to me whether I can use this part as a sink despite...
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    FET failure - physical evidence looks like pimple?

    I think the voltage being applied from an external connector is 24V, when it should be 12V. The Si4431 lists abs max VGS as ±20V, but is a 4V overvoltage really capable of causing this physical deflection in the part upon failure? That would be impressive. The current draw of the design...
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    FET failure - physical evidence looks like pimple?

    I am using a PFET (Si4431BDY) as an on/off switch for 12/24V input and it is failing once in a while. I haven't established the pattern yet as to what input conditions cause it, but the most curious part is that after the failure, there is a physical bump on top of the Si4431 that looks just...
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    boundary scan (JTAG) does not find xilinx FPGA

    sorry to revive an antiquated thread, but i have a similar situation to the OP. i'm using a spartan 3E series FPGA (XC3S250E-4TQG144C) with the recommended xilinx prom XCF02SVOG20C. when i connect with the iMpact tool, the boundary scan does not find either device. i get this error...
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    stitching via size vs other vias ?

    In this particular situation I am trying to adhere to the layout guidelines provided in the datasheets for parts like the LT3480, which shows 18+ gnd vias as a thermal conduction path to the gnd plane. I believe the main goal is to establish as low inductance as possible in the return path and...
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    stitching via size vs other vias ?

    I'm working on a design that uses a 19.7mil/0.5mm drill via for most signals and a 28mil/0.7mm drill via for higher current lines. I'd like to add some stitching vias to various ground/power planes and am curious what an appropriate via size would be for those. I want to use something...

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