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It will depend upon the magnitude of your tran violations, if magnitude is above the library limits definitely it needs to be fixed, as your library is not characterized for such a transition, and the delay value calculated by tool corresponding to such transition may be inaccurate. So, actually...
It would purely depend upon your scenario, some of which could be :
You can add additional power stripes at the hotspot.
If you found hotspot around macros (usually power hungry macros like PLL, analog macros) , you can make power rings around your macro.
If your standard cell density is huge...
Core is the inner region of a chip where you would be placing your macros, standard cells, memories, blocks in your design ( or you can say region other than IO region is core region of a chip).
W and H of a core depend upon W and H of a chip, which depends upon :
1 ) IP's used in your design...
Soft checks are performed to check the short between two or more nets through a highly resistive path, usually such shorts occur between power nets ( with different names ), connecting through a highly resistive substrate. While doing LVS, you have a option of enabling or disabling soft checks.
I agree in case of small buffers delay will be large, but while doing CTS if we give small drive strength buffers also in the buffer list, than tool is intelligent enough to select the type of buffer it wants ( like if output cap is large it will not use lower drive strength buffer and if output...
Hi,
I was reading somewhere while doing CTS, we instruct the tool to use only specefic clock tree buffers for bulding the Clock tree (usually medium drive strength clock buffers) for getting the good results.
But why do we do so, how it will help in getting bettere results ?
Hi,
I am doing a design in cadance encounter, there are no power pads in my netlist but I have designed power pads in my lef. So, how can I add power pads in my design.
You will do MMMC analysis depending upon how much voltage domains and clocks your design is having.
Some possible modes for a chip can be functional mode, sleep mode, scan mode etc.
Typically there are 3 corners max. , min. and typical.
So, for each mode you will have to do sta for each...
What are mandatory sign-off checks (is it only DRC and LVS), should we consider IR drop analysis, timing, antenna and LEC also as mandatory sign off checks ?
hi,
can you please elaborate on "Why pads should have high capacitance??" ........
---------- Post added at 13:57 ---------- Previous post was at 13:56 ----------
hi,
Physical view is also called the layout view, this is the lowest level of design abstraction in common design practice...
1. placement of cell is done in two steps:
Global placement - If tool is using partition based algorithm, then at the time of global placement tool will divide the whole area for standard cell placement into small partitions called bins.
Then the standard...
I was trying to understand that, how slotting increases the resistance against electromigration . But I found a new term "grain size", can any one tell me that what is grain size. I found this term in the underlying para:
If you reduce wire width to below the average grain size of the wire...
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