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i think is my decimation filter having error.. i dont know how to create a good lpf and decimation for my design.. my voltage is always different from my original sine wave.
thanks for the prompt reply. but when i design my functional block design using matlab-simulink i dont need to invert my signal after the integrator. i've tried inserting an inverter after my integrator but it doesnt work. i can only invert my Q or use Q bar for as my output. But i still dont...
what about analog design.. have you done any simulation of the DSM . here is my design.. but my output seems to be inverted.. anyone know if im doing anything wrong or can explain to me why my waveform is inverted.
my output bit steam when input at Vmax there should be more 1s at the top...
have anyone done any simulation of the DSM . here is my design.. but my output seems to be inverted.. anyone know if im doing anything wrong or can explain to me why my waveform is inverted.
my output bit steam when input at Vmax there should be more 1s at the top however my waveform stated...
Okie. let me start with the signal amplitude.
im using simulink sinewave block attach are the details
a amp=2V sinwave= 2*pi*1000 <-- freq = 1khz..
if i weree to perform an FFT i should be seeing 1 straight line at 1khz???
what code to use to do a FFT from the sinewave? and does the stop...
Hi all,
i've create a sigma delta modulator.
below is my schematic and output waveform..
however it was inverted? what did i do wrong?
it a 1st order sigma delta. anyone know abt sdm please help..
i've done some simulations on sigma delta ADC. but i think my output is not so correct..anyone can help me out attacedh are my design and waveforms
mainly the decimation design im not sure of.
matlab simulink
1st order sigma delta adc
input: 2V Fb=1kHz , OSR=16 times
the 1 bit DAC simply is...
Just to check. On what i'm suppose to get after designing a sigma delta ADC. If my input is a Sine Wave (analog signal).
after pass through sigma delta modulator become 1-bit data stream (anyone can further explain 1-bit data stream).
will i be getting only either bit stream of 1s and 0s or...
hi bhuvy..
i did not use much of delsig kit deisgn i used simulink to design my CT DSM .attached is my design..
anyway i found out from my design..
my digital output alway has a delay when i use smaller OSR. As OSR increases>> delay get shorter >> more closer to my analog signal .. is this...
i also need to ask if anyone have successfully tried interfacing matlab simulink with circuit level design. is that possible? i intending to create schematic design with ltspice and out bit stream to pump into my simulink Decimation filter block the derive the output. wonder if anyone have...
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