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Recent content by darshankumar

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    Radon transform in verilog

    Any Body can give suggestion for implementing Radon transform in verilog.
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    Openings in MNC in digital

    I am M.Tech in Vlsi Design and Embedded System 2012 passed out .I am doing verification of AMBA3 APB and AHB Protocol BUS using UVM.I have 4 Month Experience..
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    Looking For Asic design Verification Job

    Hi I am looking for asic design verification job. I have Knowledge on SYSTEM VERILOG VERILOG TESTBENCH METHODOLOGY (UVM) Kindly contact me if any openings @ kadarshankumar@gmail.com
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    Openings in MNC in digital

    Hi i am looking for ASIC Verification job with 4month experience .Currently working for Latest Test Bench Methodology (UVM).I hope reply from you and my email contact is kadarshankumar@gmail.com With Regards DARSHAN KUMAR
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    I am getting error please help me in cent os of synopsys tool

    Warning-[LNX_OS_VERUN] Unsupported Linux version Linux version 'CentOS release 6.3 (Final)' is not supported on 'i686' officially, assuming linux compatibility by default. Set VCS_ARCH_OVERRIDE to linux or suse32 to override. Please refer to release notes for information on supported...
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    FATAL_ERROR:Xst:Portability/export/Port_Main.h:143:1.17

    thanks for all your suggstions
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    FATAL_ERROR:Xst:Portability/export/Port_Main.h:143:1.17

    hi i am doing aes implementation on fpga .i am not synthesized for the below code. module test(output[127:0]y,input clk); reg rst; reg [383:0] tv[512:0]; reg [383:0] tmp; reg kld,ld; reg [127:0] key; reg [127:0] plain, ciph; reg [127:0] text_in; wire [127:0] text_out; wire [127:0] text_out2...
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    Unsupported Event Control Statement

    hello every one,I have written a code for AES using verilog .I am getting desired output in model sim with the same code.I have to dump on FPGA .In order i am using xilinx 10.1,it is giving error and the code is below. module test(output[127:0]y,input clk1); reg clk; reg rst; reg [383:0]...
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    help me in rotation of contents of block ram memory

    how to use parity bits for rotation
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    ERROR:HDLCompilers:27 - "da.v" line 12 Illegal redeclaration of 'dout1'

    `timescale 1ns / 1ps module sd(input clk,input en, input [7:0] din1, input [7:0] addr1, input we, output [7:0] dout1 ); parameter RAM_WIDTH =8; parameter...
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    Please send me an example too if any body is familiar with accessing bram content.

    i have read pdf files of core generator.the examples given in that are done with inference .i want examples using core generator
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    Please send me an example too if any body is familiar with accessing bram content.

    since i am new to programming of bram using core generation .how to write program in verilog
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    Please send me an example too if any body is familiar with accessing bram content.

    hi.i am doing project aes algorithm using bram.can any one help me
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