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Recent content by Darshan_Dhameliya

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    Memory cells basic documents

    Sir in http://ptm.asu.edu/ >> Nano-CMOS>> NMOS (45nm) selected but about these value..? Its predefined value. Leff 17.5nm Vth 0.18 V Vdd 1V Tox 1.1nm Rdsw 155Ohm so How to choose..? Sir, in Mentor graphic how to check which technology is available...? because my doesn't...
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    Memory cells basic documents

    Thank you sir Sir i have few question.. 1) which software i can use...? I have tanner v13.0 and mentor graphics 2) Is there any architecture is available of BIT CELL & SENSE amp And 6-T SRAM.? So i can use directly that architecture. 3) Can you send me URL or any video tutorial link..? Thank...
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    what are the W/L parameter for PMOS and NMOS

    Sure you can do that - if you know how to - but you wouldn't be able to simulate it without a corresponding simulation model. Sir what type of simulation..? I didn't understand.. I know how to design layout but can you teach me what is a necessary step and what is the minimum lembda size to...
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    develop Flash memory by microcontroller programing

    I want to design NAND flash.. but how and which interface is good and easy..
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    develop Flash memory by microcontroller programing

    I don't know how to develop Flash memory by microcontroller programing..? Is there any web site or URL for programing structure..? Is it readily available program present..? Only I know is that develop Flash memory by designing Floting gate in Mento graphics, tanner, cadence, etc.. My project...
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    Memory cells basic documents

    Hello Sir, Even I want knowledge about Flash memory and how to implement(direct layout or schematic then layout) and I have tanner v.13 *****. Thank you & Regards Darshan
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    what are the W/L parameter for PMOS and NMOS

    Thank you sir. Actually sir for my last year project I selected to design " Flash memory ". So sir for design flash memory "Floting gate" is required but I could not find floting gate transistor in PDK for schematic design. After designing schematic I can go for layout. Sir can I design...
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    what are the W/L parameter for PMOS and NMOS

    Dear Sir, I Darshan studying master in VLSI design. In my college Mentor graphic is there, in that i can't find which process technology(nm) is present. So can you help me out to find which process technology present by calculating W/L ratio. W/L= 0.32 um/0.17 um is there. And can tell me...

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