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Recent content by darockdr

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    VHDL to Schematic caaaadence flow

    Thanks kingslayer, I am having a license issue with encounter, but thank you for the steps to follow ! that was exactly what i needed. I ll get back to you as soon as i can start playing with encounter ! Best, David
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    VHDL to Schematic caaaadence flow

    Hello I have a vhdl file (behavioral .. if then ...) that i would like to synthesize with specific logic gate from my cadence Design Kit library. I am not sure where to start, it would be great if someone can direct me or show me the flow to do that . my vhdl is only combin logic but i don't...
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    CMOS level shifter 0/1.5 V to -0.75/+0.75V

    Thank you brad for the example, that was perfect !
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    CMOS level shifter 0/1.5 V to -0.75/+0.75V

    Hi, Do you guys have some design example for a CMOS level shifter 0/1.5 V to -0.75/+0.75V circuit ? Thanks a lot ! david
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    .vec spectre vector file to Eldo

    Is there a way to "convert" a spectre vector file to something that can be run with Eldo ? I have a long vector file that i need to simulate with Eldo ... Thanks, David
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    simulate compiled .so component

    simulate compiled .so component cadence Hello guys, I was given a component in a .so format (compiled verilogA is my guess) and i would like to make it a cell in virtuoso to include it in a schematic and simulate it with spectre. Do you guys know how to do that ? One told me to create a...
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    cadence VHDL AMS - ERROR (OSSHNL-116)

    Hi everyone, I have a cell "resistor" described in vhdl ams. It compiled fine and created 3 cell views : entity, behavioral and symbol I implemented the "resistor" symbol in a new cell schematic "xbar" I am trying to simulate this schematic using spectre in ADE L but I have this error...
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