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Re: Synthesis lib
I think set_clock_uncertainty is used during prelayout stage. For post layout, I am using "set_clock_propagation propagated" cmd. How much margin do we have if we use slow lib to synthesize the design?
Synthesis lib
Thanks. Is that meaning if I run STA like prime time and I get worse case timing violation for example 130 ps (clock is 4 ns), it is still ok according to your comment because there is 25% margin. is this correct?
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