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Recent content by damn

  1. D

    error in elevator code (vhdl)

    infix operator in vhdl good you solved the problem, keep it up
  2. D

    about mini project related to HDL

    do it by your self its easy
  3. D

    HDL Entry vs. Schematic Entry Tool?

    VHDL and verilog , bottom level, top level schematic
  4. D

    verilog cinvert to vhdl

    why its needed
  5. D

    need ur suggestion on this...

    hi srinivas, good to hear this news, all these years you are in problem free world, use Quartus II, Xilinx ISE, MAC,OFDM,FFT,IFFT,DTV, HDLC,Viterbi , reed solomon, ATA,IDE,CF ,in fpga and next ETHERNET,10 BT, its ok, but back end is true electronics mos, tunnel like that, good luck
  6. D

    What is the use of gray code?

    gray code glitch free used as a counter, changes only one bit, so glitch free
  7. D

    Looking for part 1 and 2 of this DC tutorial

    Re: DC tutorial many in the forum, use search
  8. D

    Need some interview question

    search google many many
  9. D

    traffic light controller

    where is the design, or means do you need combinations of states, it depends on the junction type, like 4,3,5, crosses and also depends on lanes , and ped also
  10. D

    primetime check different clock

    Re: Clock domain Crossing use synchrozer
  11. D

    The negative edge triggered FFs

    Re: FFs with Negedge!!! w.r.t to edge timing analysis. ha ha its simple
  12. D

    pipelining in verilog

    its like a bucket, one fill, next next cascaded
  13. D

    what are level shifters?

    if input is 3.3v then some voltage domain needs 5 v.,then you need ls, silimlar like max232,
  14. D

    what is Modelsim SE EE PE ??

    go for aldec rivera

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