Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Need some help confirming my thoughts/advising on the mitigation for an existing system design that is having susceptibility issues.
Side A:
Voltage Reg
Reference Ground
LVDS receiver
Outer most shield tied to earth through safety capacitors
LVDS lines shield (within the outer most shield)...
I have designed a BJT current mirror utilizing FZT658 NPN. The current source is a 150V pulse through a 5K resistor. The frequency is 80hz with a 25% duty cycle. In simulation this seems to work perfectly, in practice, the output pulse has a RC decay characteristic. I am not sure what is causing...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
