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Hi,below is the simulation settings.
I used to use the 'stb' simulation. the circuit DC point is also right under this settings. My colleagues have all reviewed this but cannot answer it. We guess it has something to do with the simulator, but not sure.
Hi,
I have a pseudo-differential amplifier and get its common mode (CMDM=1) loopgain and loop phase, which are shown below. The 2 small opamps are simple 2-stage 7-MOSFET amplifiers. Strange enough, the loop phase starts from 0 deg when differential input is 20mV, but when the input is 10mV or...
I'm testing my ultra-low VDD image sensor chip, and the on-chip LDO can provide a minimum output of 0.6V. Now I wanna further decrease the VDD to 0.4V to see if it still works. The question is how to generate this 0.4V VDD?
Current drawn from this VDD is uA level.
Thanks alot for reply.
I'm doing DC sweep simulation with cadence 5141. Now I've got V1~VX plot and V2~VX plot, from which I want to obtain the V1~V2 plot. How to do this?
I know that this is possible through exporting the data to MATLAB or Origin and replot, but can I do it with cadence spectre? THANKS
Hi,
I need a 10nA off-chip current source to provide reference current for my IC. The load is a diode-connected NMOSFET(mirror transistor). How to make it? Any devices or circuit configurations (off-chip)?
Thank you in advance.
I just added caps where there is free space. The total area is about 40000 um square. Generally, will the leakage of this one reach 1uA? My gate voltage is quite low, so I guess the gate tunneling leakage won't be that serious.
Hi mtwieg,
I'm talking about on-die decoupling caps using MOSFET caps, not ceramic ones, and I'm worrying about the the tunneling current through the gate oxide, so I wonder what's the order of magnitude.
As for IO driving, I have a 3.3V on IO ring and all digital IO cells have built-in voltage...
Hi,
My analog VDD is 0.6V(core circuit in subthreshold) and I'm using 0.18um process, and my AVDD current is on the order of 10uA, so I do care about any leakage. How to properly add some decoupling caps between AVDD and AGND?
For NMOS core device (tox is 4nm), I worry that the gate leakage...
But why thick oxide? I mean the normally used thin oxide for MOSFETs is good quality as well. Thick oxide is found in high-V IO devices and we are not sure about the effect of it in pixels.
Thank you,
An extra question is that, we found a "thick oxide(like TGO)" layer in both of our 2 reference pixel photodiode designs, so what's the role of this layer? Does it make the pixel perform better?
Hello, I'm doing the doing the pixel photodiode layout for the first time. It's a pinned-photodiode(p-sub/n-well/p+)
Should I fully cover the n-well region by ACT(active region) in layout? There are DRC and LVS errors if I do this, and if I only cover the p+ region(enclosed by n-well) with ACT...
Hello,
I am now doing the post simulation of a ring oscillator and my DRC and LVS are ok. But when it comes to PEX the problem is that, the parasitic r and c have been in the pex.netlist but their symbol cannot be seen in the calibreview generated , in which they should be res and cap...
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