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Recent content by cuiyujie

  1. C

    Help me write a code for extraction of static ram

    Simply write a behavioral array and write processes to define its rd/wr method, 1/2 port, etc. the synthesizer in FPGA will convert it to its own RAM, of course sometimes have performance degrade when it doesn't fit in the original one.
  2. C

    Information about Design For Test for ASICs

    Design for Test is big problem, there is no single complete solution for everything. If you simply want to test your own simple logic and use scan method, you can check this article: Ten Commandments of Scan Design, If you want to use BIST for memory test, it is usually provided by the vendor...
  3. C

    How to deal with a rom in module code in DC?

    I am not very sure about your problem. What are you supposed to do with your rom? If you just want to verify your design, you didn't need to care its implementation and simply model it as an array of integers or array of std_ulogic. All you need to do is in your testbench you first write it the...
  4. C

    A synthesis problem about Design Compiler

    design compiler net name You cannot make sure all the name of all your internal wires is the same as before, adapt to these changes and don't count on post simulation a lot in verification.
  5. C

    Who can tell me what difference of them? (VHDL)

    Hi, It's not clear what's dr, ad_bus_out and what you really want to implement for those 2 signals. One thing you should keep in mind is to make the sensitivitly list complete in process if you want to use process. Or else, Another way maybe just as simple as: ad_bus <= ram_bus when rd = '0'...
  6. C

    best verilog lint tool

    spyglass lint Try TransEDA VNavigator, or Novas nLint, personally I prefer Vnavigator. Good luck :wink:
  7. C

    I don't know what to do about embedded IP in simulation?

    How did you get the IP? By luck You also get a behavioral model then everything is easy. Or else you have to read the sepecification of UART and generate your own testbench for it.
  8. C

    Good combinational ATPG tools: Atalanta

    atalanta atpg download Source code inside, can revise it yourself, hehe. Disadvantage is that it requires the input format. Uploaded file: **broken link removed**
  9. C

    What's the best way to do Regression Testing?

    Any idea? Thanks!
  10. C

    Good papers for Asycronous FIFO Design

    Another! Uploaded file: **broken link removed**
  11. C

    Good papers for Asycronous FIFO Design

    Hope helps! Uploaded file: **broken link removed**
  12. C

    Looking for a book about VHDL/Verilog ASIC design

    Strong encouragement of "Reuse Methodology Manual" by Synopsys&Mentor, a must for IC engineer.
  13. C

    Please introduce some good materials for Cadence back-end to

    Openbook from Cadence is really unreadable, could anybody recommend some good introduction books, where to begin? Thanks a lot.
  14. C

    Why nobody has interest in DFT?

    Basically two methods in DFT, scan-based design and BIST; scan-based design can reach high fault coverage with little design effort, but at-speed scan cost a lot using high-end testers; BIST is widely used in memory test and became more and more popular(logicBIST) because of this.
  15. C

    Which synthesis tool to use with a FPGA ?

    Problem is from your large combinational logic for sure, check your own code and synthesis result, analyze your critical path, you can make it.
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