Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by cuiya

  1. C

    PCIe flow control question

    if I get a pcie flow control update packet posted header credit = 0 and posted data credit =0, does that mean there is no more credit available in the transmitted device??
  2. C

    ASIC Verification position tips and tools?

    Learn Specman, SystemVerilog and VMM. How to architect testbenches so it is reusable, flexible and can enable fast testcase development. Know about what a BFM, Driver, Monitor, Random Generator, Scoreboard is. Also depend on the stuff they work on you might want to read up on bus...
  3. C

    help me with verilog code

    just do: always @(a and b) always @(a or b) or use always_comb block in system verilog.
  4. C

    How to stop atomic_gen and do direct test in vmm

    use +vmm_test=<test_name> when you run the simulation <test_name> is created using vmm_macro `vmm_test_begin and `vmm_test_end. You need to read up on vmm_test in the vmm libaray manual.
See more

Part and Inventory Search

Back
Top