Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I agree with your statements when you are, in this case, at high frequencies near 500kHz to the 1MHz switching frequency. However, I have two comments:
1) The system is nonlinear and time varying at all frequencies, low and high, SSA is just a way to approximate the system as an LTI at low...
The switching frequency is 1 MHz. It is a current-mode converter. I know it is unpractical for the moment, but I am assuming that the current loop has an infinite bandwidth or at least much higher than the voltage loop so that it does not introduces any pole or phase lag in the voltage loop. I...
Thanks for the reply.
I am trying to design a fast DC-DC converter and like you mentioned, when you consider an analysis of the average small-signal quantities, it is accurate until half the switching frequency. However, in my case the crossover frequency is near/past half the switching...
Does any one know what is the effect of the switching frequency on the loop gain of a DC-DC switching converter? I know it should add phase lag in the loop gain but I am looking to find an analysis. Any pointers or references will be highly appreciated.
There is no minimum/maximum W/L specification, you can make it whatever you want. The only restriction is that W and L has their minimum lengths. Both should be specified in the PDK of your process and in few occasions in the model with parameters wmin and lmin.
I would still prefer the right one.
Two things:
1) in the right case the capacitance should be less. The capacitance due to the area is the same but you have less perimeter in total, so less sidewall capacitance.
2) It depends what comparator topology you have, but if the current mirror is an...
I would choose the one on the right since it is more square than the other. If it is square you avoid having to much effect from a gradient due to a long dimension.
Note that in both channel length is the same, it is the width that changes and the gate resistance. If the current mirror is only...
The latest models for transistors includes more factors than vbs when calculating the vth of a device. As an example, W and L will affect vth to some extent. I would say that typically the value quoted for the vtho is for minimum length lmin and wide width (maybe >10*wmin) like you would...
For the boost controller, it is necessary to have a controller with current mode because the inductor current is out of phase with the output voltage.
To choose a particular control, everyone has pros and cons. You need to give specifications such as speed, accuracy, ease of implementation...
I would go with:
X CCAABBCC X
X CCCDDCCC X
since is more symmetric.
As for the second question, since you have the source of the left transistor on a different net, their sources should not be connected. You can do that if both sources are connected to the same net such as ground. In this case...
Dummies is always recommended on the sides, where the drain and sources are. Since you are not using the devices, they can be thinner compared to the active transistors. There no physics behind my recommendation, but you can use a width size of 1.5x or 2x minimum width for the dummies. I just...
If you have a fixed area, you will have a particular mismatch on threshold voltages: dVth
In current mirror you want to have a large vgs to have a small gm as possible so the voltage mismatch dVth does not change the current that much (is like having a low gain transistor)
I am assuming here...
The idea of the common centroid is to eliminate the effects of gradients across the two transistors. To minimize the gradient effect you want to use common centroid and have a compact & modular (square) layout. It seems that your idea can work but you might end up with a layout to long in one...
If you don't have a decap, the impedance will keep increasing, meaning that when you have a current spike demanded from the load (or any current change with high frequency content) the voltage drop can be huge. It is similar to keeping IR drops low at DC but the decap does it at high...
For the NF you have to use \[{10}^{NFdB/10}\] , because is related to a power quantity.
For the gain you have to use \[{10}^{GAINdB/20}\], because it is related to a voltage quantity.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.