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shileding will be done for minimize the coupling effect,generally high freq,and analog signals are aggresser nets,these nets cause SI problems,to minimize the coupling effect we do shelding net i.e is connected to GND this will decrease the coupling cap but it increase GND cap but overall SI...
Clock Tree Synthesis
yes rst signal also treated as clock, but the specifications are not that much constrained,why this be build tree is rst signal is high fanout net.to minimize trasitions we build tree for this signals.
->why we go for upper layer for layer hopping is because during fabricatin masking is going low layer to top layer,antinna violation is main b'use of charge deposition on long nets if u go for lower layers charge will be continue flow b'use lower layer already there,if u go for upper layer...
-ve setup/hold will be there in cell library while design,
b'use those r designed with adding some delay(by delay cell) in clock path, so this will cause some delay in clk path,so thats why they add -ve setup time in library for analysis, reverce is for hold.
i think u got the point.
we have to give both importance,if u r specific u have to give hold as important.because if u have hold viol. left chip wont work,if u have setup u can decrease clk frec. to work.
HFN and CTS
yes ,generally set and reset pins are HFN out nets, to minimize insertion delay and fanout we build buffer tree during CTS.but these r not constrained much like clk in clk spec
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