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Recent content by cschen

  1. C

    What does fanout_length value pairs imply?

    Re: fanout_length Show you an example wire_load (“500”) ( resistance : 3.0 /* R per unit length*/ capacitance: 1.3 /* C per unit length */ area: 0.04 /* area per unit length */ slop: 0.15 /* extrapolation slope*/ fanout_length ( 1 , 2.1) /* fanout-length pairs */ fanout_length ( 2 , 2.5)...
  2. C

    Add Texts in Magma Blast Fusion...

    For a chip design (design w/ IO Pad), can anyone tell me how to add texts for LVS in Magma Blast Fusion?
  3. C

    Astro or SOC Encounter?

    astro encounter Which one is better? Please give me your suggestion and also the pros and cons.
  4. C

    Does P&R tools accept this verilog netlist?

    assign statements are not an issue for flat designs but could cause back annotation issues for hierarchical verilog out.
  5. C

    LVS for cell-based design

    need lvs verification Hello, I have some questions of LVS for cell-based design. 1. Since both the layout and netlist are generated by P&R tools, is it necessary to do LVS? 2. We add the bond cells of the staggered IOs in layout editor and add texts on those cells for runnung LVS...
  6. C

    TSMC Memory Compiler?

    tsmc memory generator you can browse artisan's web site (**broken link removed**) to get more specific information about the memory compiler
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