Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi
We all know that while using the SoCE to synthesis the clock tree, we have to deal with the *.ctstch file. This file specifies the three important parameters of the clock tree, the latency, the skew and the transition time. So my question is, how do these three impact the design?
As far as I...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
