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Recent content by Creese

  1. C

    problem when running nanosim-vcs co-simulation

    Hi all My tools environment is : installv3.0 , scl10.9.3 vcs2012, nanosim2012 I have already run vco of nanosim examples, it's passed. But when I run NS-VCS in tutorial of nanosim examples, there was a error after "simv +COMPILE" command: ***** Warning: Stacksize soft limit 10240 K is...
  2. C

    DFT & Synthesis: Scan clock inversion and non-unate warning

    You'd better not to use registers with different clock edges. Instead, you should generated a inverted clocks before the negedge register and then this register will be implementation into a posedge register.
  3. C

    I wannt to make a group of VLSI lowpower design

    Hi everyone, I wannt to make a group about VLSI lowpower design. Does anyone interested in these area? or if you also like to discussion topic about VLSI lowpower design, or have a Preference of manage such a group, welcome to connect with me. I'm a digital IC engineer, have a 3 years experience...
  4. C

    two synthesis runs with two separate libraries - different slack numbers

    the netlists synthesised which you used different library may be different. When you use the faster library to synthesis, some path maybe have bigger slave than the slow one, but the total slace may be better than another. If you modify the some of the path to make them have no violation, then...
  5. C

    i want a tutorial for synopsys DC

    You can use the dc user guide to improve your dc skill. I think it is the best manual for learing dc.
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