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I have implemented an I2C master in verilog, it can read/write I2C-based EEPROM like AT24C0x. I cut the I2C bus control into 4 steps : start, stop, write, read. And any operation on an I2C device can be assembled by these steps.
See
**broken link removed**
try these steps:
1. check the package of XC9572XL that u have selected in your project in ISE, PC44?
2. connect anything u need and power on.
3. run iMPACT, do not create new project, click Boundary Scan (in the left) and then Initialize the JTAG Chain (in Menu->File).
Can u find the...
how to generate a 2 khz from a 1 mhz using vhdl
Agreed with Kr,Avi.
The codes I have given above is just an example, if you want to get 64KHz, you have to write the codes by yourself.
GL!
Craftor
mentory graphics hdl designer hdl import wizard
If you want to implement a project in @ltera's FPGA, you'd better use qu(at)tus, it will save a lot of problems.
vlsi books for beginners
I have an e-book named McGraw.Hill.VHDL.Programming.by.Example.4th.Ed.pdf which is for beginners. And I began my VHDL with it. Just send me an e-mail , I will send it back to you. Craftor. craftor#126.com.
how to generate a clock
Hers is an easy example about clock division which is 50%duty cycle, hope it will help you . Craftor
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity clkdiv is
generic ( n : integer :=10);
port (
clkin ...
Here is an example about ADC0809, hope it help you . Craftor
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity ADC0809 is
port ( d : in std_logic_vector(7 downto 0);
clk,eoc : in std_logic...
vhdl 1 & integer
Well, if I want to assign values in array like:
type type_array is array(0 to N-1) of std_logic_vector(o to N-1);
signal tmp : type_array;
how should I do ?
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