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Recent content by coolrak

  1. C

    What happens in extract RC in relation to SOC encounter?

    Re: extract RC Celtic is used to do noise and crosstalk analysis. You cant use it for extraction
  2. C

    Metal layers used for power routing

    No Prasad the lowest metal is used for std cell placement. Normally the highest metal layers are used for the power routing bcoz the resistance associated will be less for the top layers
  3. C

    About DECAP filler cells used in floorplaning

    Hi Pandit, Decaps are used to provide the power, to meet the power requiremnets when the dynamic switching happens. Decaps are placed similarly how u place filler cells. Normally put where there is more switching activity .
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    DRC Clean up in Astro. Help needed

    Hi I use Astro to do P&R. I get DRC errors which need to be cleaned up. How do I do that. Astro user manual doesnt have much info. How to do search and repair in semi manual mode in Astro
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    What is timing deration in reference to ASIC flow?

    Re: timing deration To model the effects of PVT conditions on timing we specify the derating factor for the chip. This derating factor is specified in the OCV analysis mode while doing STA. It reduces the pessimism and used to model the UDSM effects of a chip for the deeper nodes You...
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    P&R Interview Questions

    In solvenet u have an application article on this. Try out
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    What tools are needed for full ASIC flow?

    Re: Encounter Encounter is used in the Industry for Physical implementation of chips. Lately lot of companies or using the tool. Its a good tool
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    P&R Interview Questions

    hi Disney, Important thing for P&R engineer is to understand timing. You can expect lot of questions on STA. And things how do you fix violations. What is OCV analysis, crosstalk avoidance. Some tool related stuff etc
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    What tools are needed for full ASIC flow?

    Re: Encounter You need PT for timing sign-off
  10. C

    What tools are needed for full ASIC flow?

    Re: Encounter To make into a full ASIC flow you need to use sign-off tools like PrimeTime for post layout STA sign-off, Caliber for DRC,LVS sign-off and some power analysis tools like voltage storm etc. You can use Encounter only for Implementation
  11. C

    Looking for tutorials and introductory notes about Astro

    Re: Astro Help I am looking for lab database. Can I get it from solvenet. I tried but i couldnt get any. Any advices
  12. C

    Tools for Static Timing Analysis

    there is one more good tools called Timecraft from Incentia. It is second best to PT
  13. C

    set_clock_uncertainty does not affect IO timing analysis

    set_clock_uncertainty set_clock_uncertainity is for skew. As per my knowledge clock jitter effect will be specified in set_clock_latency.
  14. C

    WHICH ONE IS THE BEST EDA TOOLS FOR ASIC DESIGN FLOW?

    It depends upon the designs you are doing. If you are doing high performance designs with the latest technologies Synopsys is the best bcoz Quality of results wise its the best. But Synopsys tools dont come cheap. Other option will be either Cadence or Magma. Magma is definetly ahead of...
  15. C

    Looking for tutorials and introductory notes about Astro

    Astro Help hi Everybody, I am new to Astro tool. I want to learn the tool. Can you give some links or point me to where I can get a deisgn database to run the tool. thanks in advance
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