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Recent content by CoolMember

  1. CoolMember

    What's the best VHDL/Verilog/SystemVerilog editor?

    tab width modelsim I think Textpad is a great editor in windows. nEdit is also good in linux environment.
  2. CoolMember

    highspeed ADC, digitizer,

    Hi How do you compensate low dynamic range ? Is there any specific configuration or preparations? what about 8-bit vs 10 bits that you mentioned you need? Thanks
  3. CoolMember

    VHDL/Verilog code for Echo Cancellation

    Echo Cancellation I need it too!
  4. CoolMember

    How to solder BGA parts (for FPGA) to a PCB?

    Re: BGA part soldering - Could you give me an idea about the price for soldering and checking a typical BGA device? - Do they use two different machine for soldering and testing connectivities? - Doese anyone know how much such a machine cost? (is that resonable for a small business to buy...
  5. CoolMember

    System level verification

    Where can I find the “Assertion based Design” from Harry Foster?
  6. CoolMember

    System level verification

    What do you mean by mixed mode environment jimi ?
  7. CoolMember

    System level verification

    1- For a complex system, do we need a behavioral model for the whole system? if so, how this model can help us? how should we use it? 2- How can we make sure that we've finished the verification successfully? can somebody show me a good flowchart for complex system level verification...
  8. CoolMember

    System level verification

    As you all know, driving a subsystem to a certain state ( which is a corner case) from the Top module's inputs is very difficult and sometimes it seems impossible. So what should we do for this?
  9. CoolMember

    System level verification

    Another question: What is your idea about using a special tool or language such as specman or vera instead of using verilog and its common simulators for verification In my opinion, if you want to model a design, it makes no difference that you use verilog or another lang. to do it. But if you...
  10. CoolMember

    System level verification

    Hi satya, Thanks for your comments, Does the top level testbench include a behavioral model of top level DUT? if we want to model the top level, in which level should we model it? behavioral? RTL? ...? How can we make sure that we have exercised all internal paths and functionalities when we...
  11. CoolMember

    Tools or Scripts for Integrating individual verilog modules

    If you have to integrate and link a lot of verilog module that are written by other guys with lots of interfaces you'll see that its not that easy! I know that I can do it in a text editor manualy, but I'm seeking a better way to do it. for example, if all of team members obey certain rules for...
  12. CoolMember

    System level verification

    Thanks for your replys As a case study; suppose that we have some modules and their models in verilog language, and we have already tested each of them individually and they didn't have any mismatch. Now, we link all the DUTs together and all their related models together and test them again...
  13. CoolMember

    System level verification

    Hi guys! I want you to share your expriences about system level verification. Suppose that we have some modules that have been tested individualy and they all work fine. Now we integrate them together and we want to check the whole system. What should we care about? If you have been in this...
  14. CoolMember

    How to see the simulated waveform in debussy?

    about debussy May be this is not a good question, but, does anybody know wich one of these waveform viewers is better: ModelSim, SimVision, Signalscan Debussy?! What do you think?

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