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Since you have a MUX logic between the one clock to the other clock domain , will it be optimized in synthesis . Reason am asking this is because , Async clocks will be treated as false paths. Will it be synthesized with some special care ?
Thanks
LEC is logical equivalence checking between the RTL and synthesized netlist . Functional verification will be done @ the RTL level and to run all the verification on the gate level netlist it will take more simulator time . Hence LEC is required to compare the logical equivalence between RTL and...
Yes it is Clock Domain Crossing .
Since both the clocks are the same frequency , how are we avoding the read flop from going to metastability ? Let say the clock skew is such that the read flop setup time is violated . How can we guarantee that the read flop wont go to metastability ? Point to...
Yes you are right if the TX rate is lower than the RX rate .
But if both TX and RX rate are same and if the clock are asynchronous (no control over the phase) then the simple fifo wouldnt work . RX rate should be @least 1.5 times more than the TX clock if it needs to work in asynchronous...
First thing you need to learn is setup and hold time of FF .
And then you can proceed with the method when you connect the two flops and then add the combo logic b/w the flops what are the delays associated with it.
There are so many online tutorials and synopsys Solvnet user guides , go...
Hi qieda,
The Fifo depth is correct. But i think it might not work.
Since its asynchronous domain and we dont know the clock phase difference.
From your solution , Initially the 1st data is valid for few cycles and then the data will start poping out for every clock cycle. The data will be...
From what i know , If you add the double flip flops on the data, we might not register the correct data in the other domain . Reason being its not timing closed , since the clock is asynchronous. So adding the synchronizers is not advisable . And i dont know the phase margin also . Its pure...
Hi,
Frequency of 2 clock domains are same but they are asynchronous . How do you transfer the data from one domain to other domain ? If we use FIFO what should be the depth of the FIFO ? Since both are the same clock frequency and phase relation we cant determine since it is asynchrous and...
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