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It sure did. But losing the bit[0] would make the whole design not functioning properly, so I finally had it solved by adding those 2 commands. Thanks anyway!
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I reviewed the synthesised results, and found the next stage logic using fine_even has a little problem, which makes the tool...
Thanks for reply. Log mentioned this bit is a constant will be removed. Is it ok for me to set false these two 'compile_seqmap_propagate_constants' 'compile_delete_unloaded_sequential_cells' to solve the problem?
Hello, Im new to asic, and i encountered a strange case in using logical shift.
In my RTL, I had the left logical shift to make the var 2 times multiplied. During the simulation, the results are good. Once the sythesis had finished, the LSB of 'fine_even' became high z. Meanwhile 'fine_odd' did...
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