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Re: Co simulation
Usually, if you use the CPU core embedded in FPGA, just use CPU model instead of CPU core. The FPGA provider has these models. For ex, Xilinx embed PPC405 in its FPGA.
And Xilinx has PPC405 smartmodel in its tool set.
Unless, you develop your own CPU, otherwise just use the...
synopsys installer
INSTALL_README.txt
syn_vV-2004.06-SP2_common.tar
syn_vV-2004.06-SP2_linux.tar
then follow INSTALL_README.txt step 4~6
4.Uncompress and untar the Synopsys Installer file in a separate installer directory.
% mkdir -p /usr/synopsys/synopsysinstaller
% mv...
I think you want to design a delta-sigma/ PLL, right?
U can use HDL to design A,B counter as well as accumulator.
If you are good at logic design, you also can design them by hand.
You can coding it easily, if you know how it work.
They are just 2 programmable counters.
You can find the programmable counter code on the verilog text book.
In my view, SystemC probably is good for high level modeling, but it is dump for RTL level.
Take a look at the synopsys's "Describing Systhesizable RTL in SystemC",
and you may not want to use systemC as your HW design language.
Re: Which bus interface is the best in the SoC or IP design?
If you really care the performance, use crossbar instead of AMBA, core connect or wishbone.
But it will cost you a lot.
performance => cost :P
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