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I found that the bond wire and lead inductance on the output has significant consequence. The output oscillation occurs every clock cycle. It's especially critical when the speed is high. Before it settles, the next clock comes. I add a small resistor to attenuate the oscillation. However...
Thank you very much!
I seperate the supply of digital part, latch switch and current source. Due to the parasitic capacitance, the reference vdd and gnd are interferenced during the switching time. So there is no quiet place in the chip. The changing current on the inductors makes the output...
Hi all,
I've designed a 10bit 100M current steering DAC. The simulation results using ideal voltage supply is good. But when i add simplified bond wire model(2nH inductor + 0.5Ohm resistor) on the VDD and GND. The output is totally wrong and there is a large oscillition. I add a decoupling...
psrr ldo improve
Thank you very much!
I also want to know how to achieve high psrr in high frequency for cap-less LDO. Without the large output capacitor, the high frequency psrr is really a difficult to achieve. Are there any suggestions?
Hi all,
In portable applications, usually a buck converter followed by a LDO are used to provide the power supply. The switching frequency of DC-DC converter is usually 1MHz, and that is to say the LDO should have a rather high PSRR(40-60dB) at 1MHz to minimize the output ripple of buck...
how to improve psrr
This is the psrr plot. How can i improve the psrr at high frequency? If i want to get more than 40dB psrr at 1MHz, are there any good methods?
Thank you!
ldo psrr
hi all,
How to improve the high frequency PSRR of LDO with a fixed output capacitor?
two conditions:
large output capacitor: uF
small output capacitor: nF or pF
Thank you all!
Thank you saro_k_82! You are right. If i reverse the offset, the result is really frustrated. It even can't handle 3mV.
Which topology of bandgap do you think is more robust? In the schematic R20 is a series of resistors to get different bias voltage.
Thank you all!
Add a cap between the output of opamp and vdd improves the psrr. Could you explain the reason?
Furthermore, i add a 5mV offset and the bandgap output is rised from 1.2V to 1.27V but the shape is the same when the temperatrue varies from -40 to 85 degree.
And how much the dc offset...
Thank you all!
The circuit is as follows.
I add a cap at the output node(above R20), the psrr in high frequency is improved, while the phase margin is degraded.
Is this a right way?
or are there some other good methods?
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