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Hi
I have entererd a schematic into Cadstar8. It presently consists of a
1. a sheet with microprocessor
2. a sheet with a single ethernet controller (I need two of these)
3 a sheet with a single canbus channel (I need two of these)
4 a sheet with sram and flash memory
5 a sheet with a usart...
Hi
Am I correct in assuming that both fflops are clocked from 128mhz, the connection to the D input to the first fflop is the complementary o/p of the second fflop and the Q o/p of the first fflop is connected to the D input of the second fflop.
Thanks for you help
Hi
I have two clocks in the system, 128mhz and 64mhz, I want to generate a 90 degree phase shifted 64 mhz clock. The fpga does not have a pll or dll, any advice would be greatly appreciated
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