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I have to open a lot of file as
file1.txt
file2.txt
....
file1024.txt
How to open these kind of file name with simple method in verilog?
Such as use loop for it?
thanks.
how to stop a blocking get vmm
Thanks vishalvartak and vinod_cheedella:
I got where I make the mistake.
Now I have another question. In the program block, I have run the env.run() and I triggered the env.end_test. But the simulation does not stop.
peek + channel + vmm
Thanks telantan:
But I think the difference is only the data is move out from the channel or not. Why the simulation will be blocked when using the in_chan.get() only?
Does the get() will copy the data to tran_data?
try_get vmm
Hi, what's the difference between peek and get of vmm_channel?
I try to use the code like this:
in_chan.peek(tran_data);
do_read(tran_data);
in_chan.get(tran_data);
It works.
But if I try it like this:
in_chan.get(tran_data);
do_read(tran_data);
I think the simulation was...
I am using the latest version verilog-mode. But when I use AUTOASCIIENUM. The emacs will cause CPU 99% used and nothing i can. it will never stop. I have to kill it manually.
I think you should synthesis you design with both. The SDF should have both worst and best case timing in it. To do the sta, you just select which you will use for setup or hold check.
Re: Divide by 3 Circuit
this method use the control logic on clock path. I think it is not good for ASIC design. Is it there any other method to avoid logic on clock path?
thanks
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