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Recent content by cnnprem.eee

  1. C

    How to remove top metal layers in design?

    Hi All, In my design i am using 6lm by using magma tool. I want to remove top metal layer/met6 for top level design. I want to made met 5 as top layer. How i can do it by using magma comman????? Any one guide me to do this one????????? PLZZZZZZZZZZZ Regards, Prem
  2. C

    what is mean by Gate oxide Integrity (GOI)?

    Then what is the difference between antenna violation and gate oxide integrity? In antenna violation also charge will accumulate and damage the gate oxide then same too in GOI????????????? HOW
  3. C

    what is mean by Gate oxide Integrity (GOI)?

    what is mean by Gate oxide Integrity (GOI)?
  4. C

    What is mean by Retrograde Well ?

    Hi All, What is mean by Retrograde Well and what purpose it is using in IC manufacturing ? How it is differ from other wells? do u have any diagrammatic representation of this well? please explain this ....... I searched in edaboard yet now no material is related to this is found...
  5. C

    DEEP nWELL for negative voltages

    Re: deep nwell It use high energy ion implantation Avoid heating of wafer
  6. C

    Please any one help to find out Tcomb?

  7. C

    Please any one tell how to calculate the frequency?

  8. C

    Why we are using various frequency for Functional mode and shift mode???

    Why we are using various frequency for Functional mode and shift mode??? whether physical design engineer have a mandatory work to MET the setup and hold time in both mode?????
  9. C

    For what purpose we are using Well TAP cells?

    For what purpose we are using Well TAP cells? Any one clearly explain this one Pleaseeeeeeeeee
  10. C

    180nm denotes which one Poly width or min diffusion width ?

    Which one is correct lower metal half pitch or poly width? do u have any manual please send it to me
  11. C

    Which metal layer is used for Pre and Post route signals ?

    If i am using 9lm which metal layers are used for core ring , power straps and power rail? Then clock and signal routing in which metal layer?
  12. C

    How to calculate Die size for core limited and Pad limited design?

    How to calculate Die size for core limited and Pad limited design? please any one help me to solve this type of problems
  13. C

    180nm denotes which one Poly width or min diffusion width ?

    In 180nm technology Here 180nm denotes min diffusion width or poly width? Please any body help
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